1 /* ------------------------------------------------------------------
2 * Copyright (C) 1998-2009 PacketVideo
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
18 /****************************************************************************************
19 Portions of this file are derived from the following 3GPP standard:
22 ANSI-C code for the Adaptive Multi-Rate - Wideband (AMR-WB) speech codec
23 Available from http://www.3gpp.org
25 (C) 2007, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TTA, TTC)
26 Permission to distribute, modify and use this file under the standard license
27 terms listed above has been obtained from the copyright holder.
28 ****************************************************************************************/
30 ------------------------------------------------------------------------------
34 Pathname: ./src/pvamrwbdecoder_basic_op_gcc_armv5.h
36 ------------------------------------------------------------------------------
39 ------------------------------------------------------------------------------
42 #ifndef PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H
43 #define PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H
51 #if (defined(PV_ARM_GCC_V5)||defined(PV_ARM_GCC_V4))
53 static inline int16 sub_int16(int16 var1, int16 var2)
55 register int32 L_var_out;
56 register int32 L_var_aux;
57 register int32 ra = (int32)var1;
58 register int32 rb = (int32)var2;
61 "mov %0, %2, lsl #16\n"
62 "mov %1, %3, lsl #16\n"
70 return (int16)L_var_out;
74 static inline int16 add_int16(int16 var1, int16 var2)
76 register int32 L_var_out;
77 register int32 L_var_aux;
78 register int32 ra = (int32)var1;
79 register int32 rb = (int32)var2;
82 "mov %0, %2, lsl #16\n"
83 "mov %1, %3, lsl #16\n"
91 return (int16)L_var_out;
95 static inline int32 mul_32by16(int16 hi, int16 lo, int16 n)
99 register int32 ra = (int32)hi;
100 register int32 rb = (int32)lo;
101 register int32 rc = (int32)n;
105 "smulbb %0, %2, %4\n"
106 "smulbb %1, %3, %4\n"
107 "add %0, %0, %1, asr #15\n"
119 static inline int32 sub_int32(int32 L_var1, int32 L_var2)
121 register int32 L_var_out;
122 register int32 ra = L_var1;
123 register int32 rb = L_var2;
134 static inline int32 add_int32(int32 L_var1, int32 L_var2)
136 register int32 L_var_out;
137 register int32 ra = L_var1;
138 register int32 rb = L_var2;
149 static inline int32 msu_16by16_from_int32(int32 L_var3, int16 var1, int16 var2)
151 register int32 L_var_out;
152 register int32 ra = (int32)var1;
153 register int32 rb = (int32)var2;
154 register int32 rc = L_var3;
157 "smulbb %0, %1, %2\n"
168 static inline int32 mac_16by16_to_int32(int32 L_var3, int16 var1, int16 var2)
170 register int32 L_var_out;
171 register int32 ra = (int32)var1;
172 register int32 rb = (int32)var2;
173 register int32 rc = L_var3;
176 "smulbb %0, %1, %2\n"
187 static inline int32 mul_16by16_to_int32(int16 var1, int16 var2)
189 register int32 L_var_out;
190 register int32 ra = (int32)var1;
191 register int32 rb = (int32)var2;
194 "smulbb %0, %1, %2\n"
204 static inline int16 mult_int16(int16 var1, int16 var2)
206 register int32 L_var_out;
207 register int32 ra = (int32)var1;
208 register int32 rb = (int32)var2;
211 "smulbb %0, %1, %2\n"
212 "mov %0, %0, asr #15"
217 return (int16)L_var_out;
220 static inline int16 amr_wb_round(int32 L_var1)
222 register int32 L_var_out;
223 register int32 ra = (int32)L_var1;
224 register int32 rb = (int32)0x00008000L;
228 "mov %0, %0, asr #16"
232 return (int16)L_var_out;
235 static inline int16 amr_wb_shl1_round(int32 L_var1)
237 register int32 L_var_out;
238 register int32 ra = (int32)L_var1;
239 register int32 rb = (int32)0x00008000L;
244 "mov %0, %0, asr #16"
248 return (int16)L_var_out;
252 static inline int32 fxp_mac_16by16(const int16 L_var1, const int16 L_var2, int32 L_add)
255 register int32 ra = (int32)L_var1;
256 register int32 rb = (int32)L_var2;
257 register int32 rc = (int32)L_add;
260 "smlabb %0, %1, %2, %3"
268 static inline int32 fxp_mul_16by16bb(int16 L_var1, const int16 L_var2)
271 register int32 ra = (int32)L_var1;
272 register int32 rb = (int32)L_var2;
283 #define fxp_mul_16by16(a, b) fxp_mul_16by16bb( a, b)
286 static inline int32 fxp_mul32_by_16(int32 L_var1, const int32 L_var2)
289 register int32 ra = (int32)L_var1;
290 register int32 rb = (int32)L_var2;
300 #define fxp_mul32_by_16b( a, b) fxp_mul32_by_16( a, b)
312 #endif /* PVAMRWBDECODER_BASIC_OP_GCC_ARMV5_H */