1 # Hitachi H8 testcase 'stc'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
56 ldc #0xff, ccr ; test value
57 stc ccr, r0h ; copy test value to r0h
59 test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
60 .if (sim_cpu) ; h/s/sx
61 test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
63 test_gr_a5a5 1 ; Make sure other general regs not disturbed
71 .if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
76 ldc #0x87, exr ; set exr to 0x87
77 stc exr, r0l ; retrieve and check exr value
82 test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
83 test_gr_a5a5 1 ; Make sure other general regs not disturbed
96 stc ccr, @byte_dest1:16 ; abs16 dest
98 test_gr_a5a5 0 ; Make sure other general regs not disturbed
112 stc exr, @byte_dest2:16 ; abs16 dest
114 test_gr_a5a5 0 ; Make sure other general regs not disturbed
128 stc ccr, @byte_dest3:32 ; abs32 dest
130 test_gr_a5a5 0 ; Make sure other general regs not disturbed
144 stc exr, @byte_dest4:32 ; abs32 dest
146 test_gr_a5a5 0 ; Make sure other general regs not disturbed
159 mov #byte_dest5-1, er1
161 stc ccr, @(1:16,er1) ; disp16 dest (5)
163 test_h_gr32 byte_dest5-1, er1 ; er1 still contains address
165 test_gr_a5a5 0 ; Make sure other general regs not disturbed
177 mov #byte_dest6+1, er1
179 stc exr, @(-1:16,er1) ; disp16 dest (6)
181 test_h_gr32 byte_dest6+1, er1 ; er1 still contains address
183 test_gr_a5a5 0 ; Make sure other general regs not disturbed
195 mov #byte_dest7-1, er1
197 stc ccr, @(1:32,er1) ; disp32 dest (7)
199 test_h_gr32 byte_dest7-1, er1 ; er1 still contains address
201 test_gr_a5a5 0 ; Make sure other general regs not disturbed
213 mov #byte_dest8+1, er1
215 stc exr, @(-1:32,er1) ; disp16 dest (8)
217 test_h_gr32 byte_dest8+1, er1 ; er1 still contains address
219 test_gr_a5a5 2 ; Make sure other general regs not disturbed
230 mov #byte_dest9+2, er1
232 stc ccr, @-er1 ; predecr dest (9)
234 test_h_gr32 byte_dest9 er1 ; er1 still contains address
236 test_gr_a5a5 0 ; Make sure other general regs not disturbed
248 mov #byte_dest10+2, er1
250 stc exr, @-er1 ; predecr dest (10)
252 test_h_gr32 byte_dest10, er1 ; er1 still contains address
254 test_gr_a5a5 0 ; Make sure other general regs not disturbed
266 mov #byte_dest11, er1
268 stc ccr, @er1 ; postinc dest (11)
270 test_h_gr32 byte_dest11, er1 ; er1 still contains address
272 test_gr_a5a5 0 ; Make sure other general regs not disturbed
284 mov #byte_dest12, er1
286 stc exr, @er1, exr ; postinc dest (12)
288 test_h_gr32 byte_dest12, er1 ; er1 still contains address
290 test_gr_a5a5 0 ; Make sure other general regs not disturbed
300 .if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
306 ldc er0, sbr ; set sbr to 0xaaaaaaaa
307 stc sbr, er1 ; retreive and check sbr value
309 test_h_gr32 0xaaaaaaaa er1
310 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
311 test_gr_a5a5 2 ; Make sure other general regs not disturbed
323 ldc er0, vbr ; set sbr to 0xaaaaaaaa
324 stc vbr, er1 ; retreive and check sbr value
326 test_h_gr32 0xaaaaaaaa er1
327 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
328 test_gr_a5a5 2 ; Make sure other general regs not disturbed
342 .L1: mov @byte_dest2, r0h
347 .L2: mov @byte_dest3, r0h
352 .L3: mov @byte_dest4, r0h
357 .L4: mov @byte_dest5, r0h
362 .L5: mov @byte_dest6, r0h
367 .L6: mov @byte_dest7, r0h
372 .L7: mov @byte_dest8, r0h
377 .L8: mov @byte_dest9, r0h
382 .L9: mov @byte_dest10, r0h
387 .L10: mov @byte_dest11, r0h
392 .L11: mov @byte_dest12, r0h