1 # Hitachi H8 testcase 'add.w'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
13 # Instructions tested:
14 # add.w xx:3, rd ; 0 a 0xxx rd (sx only)
15 # add.w xx:16, rd ; 7 9 1 rd imm16
16 # add.w rs, rd ; 0 9 rs rd
21 .if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
23 set_grs_a5a5 ; Fill all general regs with a fixed pattern
26 ;; add.w #xx:3,Rd ; Immediate 3-bit operand
27 add.w #7, r0 ; FIXME will not assemble yet
28 ; .word 0x0a70 ; Fake it until assembler will take it.
30 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
31 test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7
32 test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7
33 test_gr_a5a5 1 ; Make sure other general regs not disturbed
42 .if (sim_cpu) ; non-zero means h8300h, s, or sx
44 ;; add.w immediate not available in h8300 mode.
45 set_grs_a5a5 ; Fill all general regs with a fixed pattern
49 add.w #0x111, r0 ; Immediate 16-bit operand
51 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
52 test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
53 test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
54 test_gr_a5a5 1 ; Make sure other general regs not disturbed
64 set_grs_a5a5 ; Fill all general regs with a fixed pattern
69 add.w r1, r0 ; Register operand
71 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
72 test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
74 .if (sim_cpu) ; non-zero means h8300h, s, or sx
75 test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
76 test_h_gr32 0xa5a50111 er1
78 test_gr_a5a5 2 ; Make sure other general regs not disturbed