1 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
4 (MIPS16_INSN_BRANCH): Rename to...
5 (MIPS16_INSN_COND_BRANCH): ... this.
7 2010-07-03 Alan Modra <amodra@gmail.com>
9 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
10 Renumber other PPC_OPCODE defines.
12 2010-07-03 Alan Modra <amodra@gmail.com>
14 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
16 2010-06-29 Alan Modra <amodra@gmail.com>
18 * maxq.h: Delete file.
20 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
22 * ppc.h (PPC_OPCODE_E500): Define.
24 2010-05-26 Catherine Moore <clm@codesourcery.com>
26 * opcode/mips.h (INSN_MIPS16): Remove.
28 2010-04-21 Joseph Myers <joseph@codesourcery.com>
30 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
32 2010-04-15 Nick Clifton <nickc@redhat.com>
34 * alpha.h: Update copyright notice to use GPLv3.
54 * m68hc11.h: Likewise.
60 * mn10200.h: Likewise.
61 * mn10300.h: Likewise.
73 * score-datadep.h: Likewise.
74 * score-inst.h: Likewise.
76 * spu-insns.h: Likewise.
85 2010-03-25 Joseph Myers <joseph@codesourcery.com>
87 * tic6x-control-registers.h, tic6x-insn-formats.h,
88 tic6x-opcode-table.h, tic6x.h: New.
90 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
92 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
94 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
96 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
98 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
100 * ia64.h (ia64_find_opcode): Remove argument name.
101 (ia64_find_next_opcode): Likewise.
102 (ia64_dis_opcode): Likewise.
103 (ia64_free_opcode): Likewise.
104 (ia64_find_dependency): Likewise.
106 2009-11-22 Doug Evans <dje@sebabeach.org>
108 * cgen.h: Include bfd_stdint.h.
109 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
111 2009-11-18 Paul Brook <paul@codesourcery.com>
113 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
115 2009-11-17 Paul Brook <paul@codesourcery.com>
116 Daniel Jacobowitz <dan@codesourcery.com>
118 * arm.h (ARM_EXT_V6_DSP): Define.
119 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
120 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
122 2009-11-04 DJ Delorie <dj@redhat.com>
124 * rx.h (rx_decode_opcode) (mvtipl): Add.
125 (mvtcp, mvfcp, opecp): Remove.
127 2009-11-02 Paul Brook <paul@codesourcery.com>
129 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
130 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
131 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
132 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
133 FPU_ARCH_NEON_VFP_V4): Define.
135 2009-10-23 Doug Evans <dje@sebabeach.org>
137 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
138 * cgen.h: Update. Improve multi-inclusion macro name.
140 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
142 * ppc.h (PPC_OPCODE_476): Define.
144 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
146 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
148 2009-09-29 DJ Delorie <dj@redhat.com>
152 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
154 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
156 2009-09-21 Ben Elliston <bje@au.ibm.com>
158 * ppc.h (PPC_OPCODE_PPCA2): New.
160 2009-09-05 Martin Thuresson <martin@mtme.org>
162 * ia64.h (struct ia64_operand): Renamed member class to op_class.
164 2009-08-29 Martin Thuresson <martin@mtme.org>
166 * tic30.h (template): Rename type template to
167 insn_template. Updated code to use new name.
168 * tic54x.h (template): Rename type template to
171 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
173 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
175 2009-06-11 Anthony Green <green@moxielogic.com>
177 * moxie.h (MOXIE_F3_PCREL): Define.
178 (moxie_form3_opc_info): Grow.
180 2009-06-06 Anthony Green <green@moxielogic.com>
182 * moxie.h (MOXIE_F1_M): Define.
184 2009-04-15 Anthony Green <green@moxielogic.com>
188 2009-04-06 DJ Delorie <dj@redhat.com>
190 * h8300.h: Add relaxation attributes to MOVA opcodes.
192 2009-03-10 Alan Modra <amodra@bigpond.net.au>
194 * ppc.h (ppc_parse_cpu): Declare.
196 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
198 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
199 and _IMM11 for mbitclr and mbitset.
200 * score-datadep.h: Update dependency information.
202 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
204 * ppc.h (PPC_OPCODE_POWER7): New.
206 2009-02-06 Doug Evans <dje@google.com>
208 * i386.h: Add comment regarding sse* insns and prefixes.
210 2009-02-03 Sandip Matte <sandip@rmicorp.com>
212 * mips.h (INSN_XLR): Define.
213 (INSN_CHIP_MASK): Update.
215 (OPCODE_IS_MEMBER): Update.
216 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
218 2009-01-28 Doug Evans <dje@google.com>
220 * opcode/i386.h: Add multiple inclusion protection.
221 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
222 (EDI_REG_NUM): New macros.
223 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
224 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
225 (REX_PREFIX_P): New macro.
227 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
229 * ppc.h (struct powerpc_opcode): New field "deprecated".
230 (PPC_OPCODE_NOPOWER4): Delete.
232 2008-11-28 Joshua Kinard <kumba@gentoo.org>
234 * mips.h: Define CPU_R14000, CPU_R16000.
235 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
237 2008-11-18 Catherine Moore <clm@codesourcery.com>
239 * arm.h (FPU_NEON_FP16): New.
240 (FPU_ARCH_NEON_FP16): New.
242 2008-11-06 Chao-ying Fu <fu@mips.com>
244 * mips.h: Doucument '1' for 5-bit sync type.
246 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
248 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
251 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
253 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
255 2008-07-30 Michael J. Eager <eager@eagercon.com>
257 * ppc.h (PPC_OPCODE_405): Define.
258 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
260 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
262 * ppc.h (ppc_cpu_t): New typedef.
263 (struct powerpc_opcode <flags>): Use it.
264 (struct powerpc_operand <insert, extract>): Likewise.
265 (struct powerpc_macro <flags>): Likewise.
267 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
269 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
270 Update comment before MIPS16 field descriptors to mention MIPS16.
271 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
273 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
274 New bit masks and shift counts for cins and exts.
276 * mips.h: Document new field descriptors +Q.
277 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
279 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
281 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
282 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
284 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
286 * ppc.h: (PPC_OPCODE_E500MC): New.
288 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
290 * i386.h (MAX_OPERANDS): Set to 5.
291 (MAX_MNEM_SIZE): Changed to 20.
293 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
295 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
297 2008-03-09 Paul Brook <paul@codesourcery.com>
299 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
301 2008-03-04 Paul Brook <paul@codesourcery.com>
303 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
304 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
305 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
307 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
308 Nick Clifton <nickc@redhat.com>
311 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
312 with a 32-bit displacement but without the top bit of the 4th byte
315 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
317 * cr16.h (cr16_num_optab): Declared.
319 2008-02-14 Hakan Ardo <hakan@debian.org>
322 * avr.h (AVR_ISA_2xxe): Define.
324 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
326 * mips.h: Update copyright.
327 (INSN_CHIP_MASK): New macro.
328 (INSN_OCTEON): New macro.
329 (CPU_OCTEON): New macro.
330 (OPCODE_IS_MEMBER): Handle Octeon instructions.
332 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
334 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
336 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
338 * avr.h (AVR_ISA_USB162): Add new opcode set.
339 (AVR_ISA_AVR3): Likewise.
341 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
343 * mips.h (INSN_LOONGSON_2E): New.
344 (INSN_LOONGSON_2F): New.
345 (CPU_LOONGSON_2E): New.
346 (CPU_LOONGSON_2F): New.
347 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
349 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
351 * mips.h (INSN_ISA*): Redefine certain values as an
352 enumeration. Update comments.
353 (mips_isa_table): New.
354 (ISA_MIPS*): Redefine to match enumeration.
355 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
358 2007-08-08 Ben Elliston <bje@au.ibm.com>
360 * ppc.h (PPC_OPCODE_PPCPS): New.
362 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
364 * m68k.h: Document j K & E.
366 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
368 * cr16.h: New file for CR16 target.
370 2007-05-02 Alan Modra <amodra@bigpond.net.au>
372 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
374 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
376 * m68k.h (mcfisa_c): New.
377 (mcfusp, mcf_mask): Adjust.
379 2007-04-20 Alan Modra <amodra@bigpond.net.au>
381 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
382 (num_powerpc_operands): Declare.
383 (PPC_OPERAND_SIGNED et al): Redefine as hex.
384 (PPC_OPERAND_PLUS1): Define.
386 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
388 * i386.h (REX_MODE64): Renamed to ...
390 (REX_EXTX): Renamed to ...
392 (REX_EXTY): Renamed to ...
394 (REX_EXTZ): Renamed to ...
397 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
399 * i386.h: Add entries from config/tc-i386.h and move tables
400 to opcodes/i386-opc.h.
402 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
404 * i386.h (FloatDR): Removed.
405 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
407 2007-03-01 Alan Modra <amodra@bigpond.net.au>
409 * spu-insns.h: Add soma double-float insns.
411 2007-02-20 Thiemo Seufer <ths@mips.com>
412 Chao-Ying Fu <fu@mips.com>
414 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
415 (INSN_DSPR2): Add flag for DSP R2 instructions.
416 (M_BALIGN): New macro.
418 2007-02-14 Alan Modra <amodra@bigpond.net.au>
420 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
421 and Seg3ShortFrom with Shortform.
423 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
426 * i386.h (i386_optab): Put the real "test" before the pseudo
429 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
431 * m68k.h (m68010up): OR fido_a.
433 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
435 * m68k.h (fido_a): New.
437 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
439 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
440 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
443 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
445 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
447 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
449 * score-inst.h (enum score_insn_type): Add Insn_internal.
451 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
452 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
453 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
454 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
455 Alan Modra <amodra@bigpond.net.au>
457 * spu-insns.h: New file.
460 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
462 * ppc.h (PPC_OPCODE_CELL): Define.
464 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
466 * i386.h : Modify opcode to support for the change in POPCNT opcode
467 in amdfam10 architecture.
469 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
471 * i386.h: Replace CpuMNI with CpuSSSE3.
473 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
474 Joseph Myers <joseph@codesourcery.com>
475 Ian Lance Taylor <ian@wasabisystems.com>
476 Ben Elliston <bje@wasabisystems.com>
478 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
480 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
482 * score-datadep.h: New file.
483 * score-inst.h: New file.
485 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
487 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
488 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
491 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
492 Michael Meissner <michael.meissner@amd.com>
494 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
496 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
498 * i386.h (i386_optab): Add "nop" with memory reference.
500 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
502 * i386.h (i386_optab): Update comment for 64bit NOP.
504 2006-06-06 Ben Elliston <bje@au.ibm.com>
505 Anton Blanchard <anton@samba.org>
507 * ppc.h (PPC_OPCODE_POWER6): Define.
510 2006-06-05 Thiemo Seufer <ths@mips.com>
512 * mips.h: Improve description of MT flags.
514 2006-05-25 Richard Sandiford <richard@codesourcery.com>
516 * m68k.h (mcf_mask): Define.
518 2006-05-05 Thiemo Seufer <ths@mips.com>
519 David Ung <davidu@mips.com>
521 * mips.h (enum): Add macro M_CACHE_AB.
523 2006-05-04 Thiemo Seufer <ths@mips.com>
524 Nigel Stephens <nigel@mips.com>
525 David Ung <davidu@mips.com>
527 * mips.h: Add INSN_SMARTMIPS define.
529 2006-04-30 Thiemo Seufer <ths@mips.com>
530 David Ung <davidu@mips.com>
532 * mips.h: Defines udi bits and masks. Add description of
533 characters which may appear in the args field of udi
536 2006-04-26 Thiemo Seufer <ths@networkno.de>
538 * mips.h: Improve comments describing the bitfield instruction
541 2006-04-26 Julian Brown <julian@codesourcery.com>
543 * arm.h (FPU_VFP_EXT_V3): Define constant.
544 (FPU_NEON_EXT_V1): Likewise.
545 (FPU_VFP_HARD): Update.
546 (FPU_VFP_V3): Define macro.
547 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
549 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
551 * avr.h (AVR_ISA_PWMx): New.
553 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
555 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
556 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
557 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
558 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
559 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
561 2006-03-10 Paul Brook <paul@codesourcery.com>
563 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
565 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
567 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
568 first. Correct mask of bb "B" opcode.
570 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
572 * i386.h (i386_optab): Support Intel Merom New Instructions.
574 2006-02-24 Paul Brook <paul@codesourcery.com>
576 * arm.h: Add V7 feature bits.
578 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
580 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
582 2006-01-31 Paul Brook <paul@codesourcery.com>
583 Richard Earnshaw <rearnsha@arm.com>
585 * arm.h: Use ARM_CPU_FEATURE.
586 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
587 (arm_feature_set): Change to a structure.
588 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
589 ARM_FEATURE): New macros.
591 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
593 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
594 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
595 (ADD_PC_INCR_OPCODE): Don't define.
597 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
600 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
602 2005-11-14 David Ung <davidu@mips.com>
604 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
605 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
606 save/restore encoding of the args field.
608 2005-10-28 Dave Brolley <brolley@redhat.com>
610 Contribute the following changes:
611 2005-02-16 Dave Brolley <brolley@redhat.com>
613 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
614 cgen_isa_mask_* to cgen_bitset_*.
617 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
619 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
620 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
621 (CGEN_CPU_TABLE): Make isas a ponter.
623 2003-09-29 Dave Brolley <brolley@redhat.com>
625 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
626 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
627 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
629 2002-12-13 Dave Brolley <brolley@redhat.com>
631 * cgen.h (symcat.h): #include it.
632 (cgen-bitset.h): #include it.
633 (CGEN_ATTR_VALUE_TYPE): Now a union.
634 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
635 (CGEN_ATTR_ENTRY): 'value' now unsigned.
636 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
637 * cgen-bitset.h: New file.
639 2005-09-30 Catherine Moore <clm@cm00re.com>
643 2005-10-24 Jan Beulich <jbeulich@novell.com>
645 * ia64.h (enum ia64_opnd): Move memory operand out of set of
648 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
650 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
651 Add FLAG_STRICT to pa10 ftest opcode.
653 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
655 * hppa.h (pa_opcodes): Remove lha entries.
657 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
659 * hppa.h (FLAG_STRICT): Revise comment.
660 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
661 before corresponding pa11 opcodes. Add strict pa10 register-immediate
664 2005-09-30 Catherine Moore <clm@cm00re.com>
668 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
670 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
672 2005-09-06 Chao-ying Fu <fu@mips.com>
674 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
675 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
677 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
678 (INSN_ASE_MASK): Update to include INSN_MT.
679 (INSN_MT): New define for MT ASE.
681 2005-08-25 Chao-ying Fu <fu@mips.com>
683 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
684 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
685 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
686 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
687 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
688 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
690 (INSN_DSP): New define for DSP ASE.
692 2005-08-18 Alan Modra <amodra@bigpond.net.au>
696 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
698 * ppc.h (PPC_OPCODE_E300): Define.
700 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
702 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
704 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
707 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
710 2005-07-27 Jan Beulich <jbeulich@novell.com>
712 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
713 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
714 Add movq-s as 64-bit variants of movd-s.
716 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
718 * hppa.h: Fix punctuation in comment.
720 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
721 implicit space-register addressing. Set space-register bits on opcodes
722 using implicit space-register addressing. Add various missing pa20
723 long-immediate opcodes. Remove various opcodes using implicit 3-bit
724 space-register addressing. Use "fE" instead of "fe" in various
727 2005-07-18 Jan Beulich <jbeulich@novell.com>
729 * i386.h (i386_optab): Operands of aam and aad are unsigned.
731 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
733 * i386.h (i386_optab): Support Intel VMX Instructions.
735 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
737 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
739 2005-07-05 Jan Beulich <jbeulich@novell.com>
741 * i386.h (i386_optab): Add new insns.
743 2005-07-01 Nick Clifton <nickc@redhat.com>
745 * sparc.h: Add typedefs to structure declarations.
747 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
750 * i386.h (i386_optab): Update comments for 64bit addressing on
751 mov. Allow 64bit addressing for mov and movq.
753 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
755 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
756 respectively, in various floating-point load and store patterns.
758 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
760 * hppa.h (FLAG_STRICT): Correct comment.
761 (pa_opcodes): Update load and store entries to allow both PA 1.X and
762 PA 2.0 mneumonics when equivalent. Entries with cache control
763 completers now require PA 1.1. Adjust whitespace.
765 2005-05-19 Anton Blanchard <anton@samba.org>
767 * ppc.h (PPC_OPCODE_POWER5): Define.
769 2005-05-10 Nick Clifton <nickc@redhat.com>
771 * Update the address and phone number of the FSF organization in
772 the GPL notices in the following files:
773 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
774 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
775 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
776 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
777 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
778 tic54x.h, tic80.h, v850.h, vax.h
780 2005-05-09 Jan Beulich <jbeulich@novell.com>
782 * i386.h (i386_optab): Add ht and hnt.
784 2005-04-18 Mark Kettenis <kettenis@gnu.org>
786 * i386.h: Insert hyphens into selected VIA PadLock extensions.
787 Add xcrypt-ctr. Provide aliases without hyphens.
789 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
791 Moved from ../ChangeLog
793 2005-04-12 Paul Brook <paul@codesourcery.com>
794 * m88k.h: Rename psr macros to avoid conflicts.
796 2005-03-12 Zack Weinberg <zack@codesourcery.com>
797 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
798 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
801 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
802 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
803 Remove redundant instruction types.
804 (struct argument): X_op - new field.
805 (struct cst4_entry): Remove.
806 (no_op_insn): Declare.
808 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
809 * crx.h (enum argtype): Rename types, remove unused types.
811 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
812 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
813 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
814 (enum operand_type): Rearrange operands, edit comments.
815 replace us<N> with ui<N> for unsigned immediate.
816 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
817 displacements (respectively).
818 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
819 (instruction type): Add NO_TYPE_INS.
820 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
821 (operand_entry): New field - 'flags'.
822 (operand flags): New.
824 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
825 * crx.h (operand_type): Remove redundant types i3, i4,
827 Add new unsigned immediate types us3, us4, us5, us16.
829 2005-04-12 Mark Kettenis <kettenis@gnu.org>
831 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
832 adjust them accordingly.
834 2005-04-01 Jan Beulich <jbeulich@novell.com>
836 * i386.h (i386_optab): Add rdtscp.
838 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
840 * i386.h (i386_optab): Don't allow the `l' suffix for moving
841 between memory and segment register. Allow movq for moving between
842 general-purpose register and segment register.
844 2005-02-09 Jan Beulich <jbeulich@novell.com>
847 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
848 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
851 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
853 * m68k.h (m68008, m68ec030, m68882): Remove.
855 (cpu_m68k, cpu_cf): New.
856 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
857 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
859 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
861 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
862 * cgen.h (enum cgen_parse_operand_type): Add
863 CGEN_PARSE_OPERAND_SYMBOLIC.
865 2005-01-21 Fred Fish <fnf@specifixinc.com>
867 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
868 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
869 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
871 2005-01-19 Fred Fish <fnf@specifixinc.com>
873 * mips.h (struct mips_opcode): Add new pinfo2 member.
874 (INSN_ALIAS): New define for opcode table entries that are
875 specific instances of another entry, such as 'move' for an 'or'
877 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
878 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
880 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
882 * mips.h (CPU_RM9000): Define.
883 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
885 2004-11-25 Jan Beulich <jbeulich@novell.com>
887 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
888 to/from test registers are illegal in 64-bit mode. Add missing
889 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
890 (previously one had to explicitly encode a rex64 prefix). Re-enable
891 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
892 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
894 2004-11-23 Jan Beulich <jbeulich@novell.com>
896 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
897 available only with SSE2. Change the MMX additions introduced by SSE
898 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
899 instructions by their now designated identifier (since combining i686
900 and 3DNow! does not really imply 3DNow!A).
902 2004-11-19 Alan Modra <amodra@bigpond.net.au>
904 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
905 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
907 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
908 Vineet Sharma <vineets@noida.hcltech.com>
910 * maxq.h: New file: Disassembly information for the maxq port.
912 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
914 * i386.h (i386_optab): Put back "movzb".
916 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
918 * cris.h (enum cris_insn_version_usage): Tweak formatting and
919 comments. Remove member cris_ver_sim. Add members
920 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
921 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
922 (struct cris_support_reg, struct cris_cond15): New types.
923 (cris_conds15): Declare.
924 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
925 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
926 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
927 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
928 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
931 2004-11-04 Jan Beulich <jbeulich@novell.com>
933 * i386.h (sldx_Suf): Remove.
934 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
935 (q_FP): Define, implying no REX64.
936 (x_FP, sl_FP): Imply FloatMF.
937 (i386_optab): Split reg and mem forms of moving from segment registers
938 so that the memory forms can ignore the 16-/32-bit operand size
939 distinction. Adjust a few others for Intel mode. Remove *FP uses from
940 all non-floating-point instructions. Unite 32- and 64-bit forms of
941 movsx, movzx, and movd. Adjust floating point operations for the above
942 changes to the *FP macros. Add DefaultSize to floating point control
943 insns operating on larger memory ranges. Remove left over comments
944 hinting at certain insns being Intel-syntax ones where the ones
945 actually meant are already gone.
947 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
949 * crx.h: Add COPS_REG_INS - Coprocessor Special register
952 2004-09-30 Paul Brook <paul@codesourcery.com>
954 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
955 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
957 2004-09-11 Theodore A. Roth <troth@openavr.org>
959 * avr.h: Add support for
960 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
962 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
964 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
966 2004-08-24 Dmitry Diky <diwil@spec.ru>
968 * msp430.h (msp430_opc): Add new instructions.
969 (msp430_rcodes): Declare new instructions.
970 (msp430_hcodes): Likewise..
972 2004-08-13 Nick Clifton <nickc@redhat.com>
975 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
978 2004-08-30 Michal Ludvig <mludvig@suse.cz>
980 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
982 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
984 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
986 2004-07-21 Jan Beulich <jbeulich@novell.com>
988 * i386.h: Adjust instruction descriptions to better match the
991 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
993 * arm.h: Remove all old content. Replace with architecture defines
994 from gas/config/tc-arm.c.
996 2004-07-09 Andreas Schwab <schwab@suse.de>
998 * m68k.h: Fix comment.
1000 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1004 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1006 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1008 2004-05-24 Peter Barada <peter@the-baradas.com>
1010 * m68k.h: Add 'size' to m68k_opcode.
1012 2004-05-05 Peter Barada <peter@the-baradas.com>
1014 * m68k.h: Switch from ColdFire chip name to core variant.
1016 2004-04-22 Peter Barada <peter@the-baradas.com>
1018 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1019 descriptions for new EMAC cases.
1020 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1021 handle Motorola MAC syntax.
1022 Allow disassembly of ColdFire V4e object files.
1024 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1026 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1028 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1030 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1032 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1034 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1036 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1038 * i386.h (i386_optab): Added xstore/xcrypt insns.
1040 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1042 * h8300.h (32bit ldc/stc): Add relaxing support.
1044 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1046 * h8300.h (BITOP): Pass MEMRELAX flag.
1048 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1050 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1053 For older changes see ChangeLog-9103
1059 version-control: never