sim/testsuite/sim/sh/fmul.s

   1 # sh testcase for fmul
   2 # mach: sh
   3 # as(sh):       -defsym sim_cpu=0
   4
   5         .include "testutils.inc"
   6
   7         .macro init
   8         fldi0 fr0
   9         fldi1 fr1
  10         fldi1 fr2
  11         fadd fr2, fr2
  12         .endm
  13
  14         start
  15 fmul_single:
  16         set_grs_a5a5
  17         set_fprs_a5a5
  18         # 0.0 * 0.0 = 0.0.
  19         init
  20         fmul    fr0, fr0
  21         assert_fpreg_i  0, fr0
  22
  23         # 0.0 * 1.0 = 0.0.
  24         init
  25         fmul    fr1, fr0
  26         assert_fpreg_i  0, fr0
  27
  28         # 1.0 * 0.0 = 0.0.
  29         init
  30         fmul    fr0, fr1
  31         assert_fpreg_i  0, fr1
  32
  33         # 1.0 * 1.0 = 1.0.
  34         init
  35         fmul    fr1, fr1
  36         assert_fpreg_i  1, fr1
  37
  38         # 2.0 * 1.0 = 2.0.
  39         init
  40         fmul    fr2, fr1
  41         assert_fpreg_i  2, fr1
  42
  43         test_grs_a5a5
  44         assert_fpreg_i  0, fr0
  45         assert_fpreg_i  2, fr1
  46         assert_fpreg_i  2, fr2
  47         test_fpr_a5a5   fr3
  48         test_fpr_a5a5   fr4
  49         test_fpr_a5a5   fr5
  50         test_fpr_a5a5   fr6
  51         test_fpr_a5a5   fr7
  52         test_fpr_a5a5   fr8
  53         test_fpr_a5a5   fr9
  54         test_fpr_a5a5   fr10
  55         test_fpr_a5a5   fr11
  56         test_fpr_a5a5   fr12
  57         test_fpr_a5a5   fr13
  58         test_fpr_a5a5   fr14
  59         test_fpr_a5a5   fr15
  60
  61         .macro dinit
  62         fldi0 fr0
  63         fldi1 fr2
  64         fldi1 fr4
  65         single_prec
  66         fadd fr4, fr4
  67         double_prec
  68         _s2d fr0, dr0
  69         _s2d fr2, dr2
  70         _s2d fr4, dr4
  71         .endm
  72
  73 fmul_double:
  74         double_prec
  75         # 0.0 * 0.0 = 0.0.
  76         dinit
  77         fmul    dr0, dr0
  78         assert_dpreg_i  0, dr0
  79
  80         # 0.0 * 1.0 = 0.0.
  81         dinit
  82         fmul    dr2, dr0
  83         assert_dpreg_i  0, dr0
  84
  85         # 1.0 * 0.0 = 0.0.
  86         dinit
  87         fmul    dr0, dr2
  88         assert_dpreg_i  0, dr2
  89
  90         # 1.0 * 1.0 = 1.0.
  91         dinit
  92         fmul    dr2, dr2
  93         assert_dpreg_i  1, dr2
  94
  95         # 2.0 * 1.0 = 2.0.
  96         dinit
  97         fmul    dr4, dr2
  98         assert_dpreg_i  2, dr2
  99
 100         test_grs_a5a5
 101         assert_dpreg_i  0, dr0
 102         assert_dpreg_i  2, dr2
 103         assert_dpreg_i  2, dr4
 104         test_fpr_a5a5   fr6
 105         test_fpr_a5a5   fr7
 106         test_fpr_a5a5   fr8
 107         test_fpr_a5a5   fr9
 108         test_fpr_a5a5   fr10
 109         test_fpr_a5a5   fr11
 110         test_fpr_a5a5   fr12
 111         test_fpr_a5a5   fr13
 112         test_fpr_a5a5   fr14
 113         test_fpr_a5a5   fr15
 114
 115         pass
 116         exit 0