1 # Hitachi H8 testcase 'shll'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
18 word_dest: .word 0xa5a5
20 long_dest: .long 0xa5a5a5a5
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
28 shll.b r0l ; shift left logical by one
31 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
35 test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
37 test_h_gr32 0xa5a5a54a er0
39 test_gr_a5a5 1 ; Make sure other general regs not disturbed
48 set_grs_a5a5 ; Fill all general regs with a fixed pattern
51 shll.b #2, r0l ; shift left logical by two
54 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
59 test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
61 test_h_gr32 0xa5a5a594 er0
63 test_gr_a5a5 1 ; Make sure other general regs not disturbed
73 set_grs_a5a5 ; Fill all general regs with a fixed pattern
76 shll.b #4, r0l ; shift left logical by four
79 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
83 test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000
84 test_h_gr32 0xa5a5a550 er0
86 test_gr_a5a5 1 ; Make sure other general regs not disturbed
95 set_grs_a5a5 ; Fill all general regs with a fixed pattern
99 shll.b r0h, r0l ; shift left logical by register value
101 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
105 test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000
106 test_h_gr32 0xa5a505a0 er0
108 test_gr_a5a5 1 ; Make sure other general regs not disturbed
117 .if (sim_cpu) ; Not available in h8300 mode
119 set_grs_a5a5 ; Fill all general regs with a fixed pattern
122 shll.w r0 ; shift left logical by one
125 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
129 test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
130 test_h_gr32 0xa5a54b4a er0
132 test_gr_a5a5 1 ; Make sure other general regs not disturbed
141 set_grs_a5a5 ; Fill all general regs with a fixed pattern
144 shll.w #2, r0 ; shift left logical by two
147 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
151 test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
152 test_h_gr32 0xa5a59694 er0
154 test_gr_a5a5 1 ; Make sure other general regs not disturbed
162 .if (sim_cpu == h8sx)
164 set_grs_a5a5 ; Fill all general regs with a fixed pattern
167 shll.w #4, r0 ; shift left logical by four
170 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
174 test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
175 test_h_gr32 0xa5a55a50 er0
177 test_gr_a5a5 1 ; Make sure other general regs not disturbed
186 set_grs_a5a5 ; Fill all general regs with a fixed pattern
189 shll.w #8, r0 ; shift left logical by eight
192 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
196 test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
197 test_h_gr32 0xa5a5a500 er0
199 test_gr_a5a5 1 ; Make sure other general regs not disturbed
208 set_grs_a5a5 ; Fill all general regs with a fixed pattern
212 shll.w r0h, r0 ; shift left logical by register value
214 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
218 test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000
219 test_h_gr32 0xa5a5b4a0 er0
221 test_gr_a5a5 1 ; Make sure other general regs not disturbed
231 set_grs_a5a5 ; Fill all general regs with a fixed pattern
234 shll.l er0 ; shift left logical by one
237 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
241 ; 1010 0101 1010 0101 1010 0101 1010 0101
242 ; -> 0100 1011 0100 1011 0100 1011 0100 1010
243 test_h_gr32 0x4b4b4b4a er0
245 test_gr_a5a5 1 ; Make sure other general regs not disturbed
254 set_grs_a5a5 ; Fill all general regs with a fixed pattern
257 shll.l #2, er0 ; shift left logical by two
260 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
264 ; 1010 0101 1010 0101 1010 0101 1010 0101
265 ; -> 1001 0110 1001 0110 1001 0110 1001 0100
266 test_h_gr32 0x96969694 er0
268 test_gr_a5a5 1 ; Make sure other general regs not disturbed
276 .if (sim_cpu == h8sx)
278 set_grs_a5a5 ; Fill all general regs with a fixed pattern
281 shll.l #4, er0 ; shift left logical by four
284 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
288 ; 1010 0101 1010 0101 1010 0101 1010 0101
289 ; -> 0101 1010 0101 1010 0101 1010 0101 0000
290 test_h_gr32 0x5a5a5a50 er0
292 test_gr_a5a5 1 ; Make sure other general regs not disturbed
301 set_grs_a5a5 ; Fill all general regs with a fixed pattern
304 shll.l #8, er0 ; shift left logical by eight
307 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
311 test_h_gr16 0xa500 r0
312 ; 1010 0101 1010 0101 1010 0101 1010 0101
313 ; -> 1010 0101 1010 0101 1010 0101 0000 0000
314 test_h_gr32 0xa5a5a500 er0
316 test_gr_a5a5 1 ; Make sure other general regs not disturbed
325 set_grs_a5a5 ; Fill all general regs with a fixed pattern
328 shll.l #16, er0 ; shift left logical by sixteen
331 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
335 ; 1010 0101 1010 0101 1010 0101 1010 0101
336 ;; -> 1010 0101 1010 0101 0000 0000 0000 0000
337 test_h_gr32 0xa5a50000 er0
339 test_gr_a5a5 1 ; Make sure other general regs not disturbed
348 set_grs_a5a5 ; Fill all general regs with a fixed pattern
352 shll.l r1l, er0 ; shift left logical by register value
354 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
358 ; 1010 0101 1010 0101 1010 0101 1010 0101
359 ; -> 1011 0100 1011 0100 1011 0100 1010 0000
360 test_h_gr32 0xb4b4b4a0 er0
362 test_h_gr32 0xa5a5a505 er1
363 test_gr_a5a5 2 ; Make sure other general regs not disturbed