1 # Hitachi H8 testcase 'shar'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
18 word_dest: .word 0xa5a5
20 long_dest: .long 0xa5a5a5a5
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
28 shar.b r0l ; shift right arithmetic by one
31 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
36 test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
38 test_h_gr32 0xa5a5a5d2 er0
40 test_gr_a5a5 1 ; Make sure other general regs not disturbed
50 set_grs_a5a5 ; Fill all general regs with a fixed pattern
54 shar.b @er0 ; shift right arithmetic by one, indirect
58 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
63 test_h_gr32 byte_dest er0
64 test_gr_a5a5 1 ; Make sure other general regs not disturbed
71 ; 1010 0101 -> 1101 0010
72 cmp.b #0xd2, @byte_dest
76 mov.b #0xa5, @byte_dest
79 set_grs_a5a5 ; Fill all general regs with a fixed pattern
83 shar.b @er0+ ; shift right arithmetic by one, postinc
88 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
93 test_h_gr32 byte_dest+1 er0
94 test_gr_a5a5 1 ; Make sure other general regs not disturbed
101 ; 1010 0101 -> 1101 0010
102 cmp.b #0xd2, @byte_dest
106 mov.b #0xa5, @byte_dest
109 set_grs_a5a5 ; Fill all general regs with a fixed pattern
113 shar.b @er0- ; shift right arithmetic by one, postdec
118 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
123 test_h_gr32 byte_dest-1 er0
124 test_gr_a5a5 1 ; Make sure other general regs not disturbed
131 ; 1010 0101 -> 1101 0010
132 cmp.b #0xd2, @byte_dest
136 mov.b #0xa5, @byte_dest
139 set_grs_a5a5 ; Fill all general regs with a fixed pattern
142 mov #byte_dest-1, er0
143 shar.b @+er0 ; shift right arithmetic by one, preinc
148 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
153 test_h_gr32 byte_dest er0
154 test_gr_a5a5 1 ; Make sure other general regs not disturbed
161 ; 1010 0101 -> 1101 0010
162 cmp.b #0xd2, @byte_dest
166 mov.b #0xa5, @byte_dest
169 set_grs_a5a5 ; Fill all general regs with a fixed pattern
172 mov #byte_dest+1, er0
173 shar.b @-er0 ; shift right arithmetic by one, predec
178 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
183 test_h_gr32 byte_dest er0
184 test_gr_a5a5 1 ; Make sure other general regs not disturbed
191 ; 1010 0101 -> 1101 0010
192 cmp.b #0xd2, @byte_dest
196 mov.b #0xa5, @byte_dest
199 set_grs_a5a5 ; Fill all general regs with a fixed pattern
202 mov #byte_dest-2, er0
203 shar.b @(2:2, er0) ; shift right arithmetic by one, disp2
208 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
213 test_h_gr32 byte_dest-2 er0
214 test_gr_a5a5 1 ; Make sure other general regs not disturbed
221 ; 1010 0101 -> 1101 0010
222 cmp.b #0xd2, @byte_dest
226 mov.b #0xa5, @byte_dest
229 set_grs_a5a5 ; Fill all general regs with a fixed pattern
232 mov #byte_dest-44, er0
233 shar.b @(44:16, er0) ; shift right arithmetic by one, disp16
239 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
244 test_h_gr32 byte_dest-44 er0
245 test_gr_a5a5 1 ; Make sure other general regs not disturbed
252 ; 1010 0101 -> 1101 0010
253 cmp.b #0xd2, @byte_dest
257 mov.b #0xa5, @byte_dest
260 set_grs_a5a5 ; Fill all general regs with a fixed pattern
263 mov #byte_dest-666, er0
264 shar.b @(666:32, er0) ; shift right arithmetic by one, disp32
270 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
275 test_h_gr32 byte_dest-666 er0
276 test_gr_a5a5 1 ; Make sure other general regs not disturbed
283 ; 1010 0101 -> 1101 0010
284 cmp.b #0xd2, @byte_dest
288 mov.b #0xa5, @byte_dest
291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
294 shar.b @byte_dest:16 ; shift right arithmetic by one, abs16
299 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
312 ; 1010 0101 -> 1101 0010
313 cmp.b #0xd2, @byte_dest
317 mov.b #0xa5, @byte_dest
320 set_grs_a5a5 ; Fill all general regs with a fixed pattern
323 shar.b @byte_dest:32 ; shift right arithmetic by one, abs32
328 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
333 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
341 ; 1010 0101 -> 1101 0010
342 cmp.b #0xd2, @byte_dest
346 mov.b #0xa5, @byte_dest
350 set_grs_a5a5 ; Fill all general regs with a fixed pattern
353 shar.b #2, r0l ; shift right arithmetic by two
356 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
360 test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001
362 test_h_gr32 0xa5a5a5e9 er0
364 test_gr_a5a5 1 ; Make sure other general regs not disturbed
372 .if (sim_cpu == h8sx)
374 set_grs_a5a5 ; Fill all general regs with a fixed pattern
378 shar.b #2, @er0 ; shift right arithmetic by two, indirect
382 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
387 test_h_gr32 byte_dest er0
388 test_gr_a5a5 1 ; Make sure other general regs not disturbed
395 ; 1010 0101 -> 1110 1001
396 cmp.b #0xe9, @byte_dest
400 mov.b #0xa5, @byte_dest
403 set_grs_a5a5 ; Fill all general regs with a fixed pattern
407 shar.b #2, @er0+ ; shift right arithmetic by two, postinc
412 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
417 test_h_gr32 byte_dest+1 er0
418 test_gr_a5a5 1 ; Make sure other general regs not disturbed
425 ; 1010 0101 -> 1110 1001
426 cmp.b #0xe9, @byte_dest
430 mov.b #0xa5, @byte_dest
433 set_grs_a5a5 ; Fill all general regs with a fixed pattern
437 shar.b #2, @er0- ; shift right arithmetic by two, postdec
442 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
447 test_h_gr32 byte_dest-1 er0
448 test_gr_a5a5 1 ; Make sure other general regs not disturbed
455 ; 1010 0101 -> 1110 1001
456 cmp.b #0xe9, @byte_dest
460 mov.b #0xa5, @byte_dest
463 set_grs_a5a5 ; Fill all general regs with a fixed pattern
466 mov #byte_dest-1, er0
467 shar.b #2, @+er0 ; shift right arithmetic by two, preinc
472 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
477 test_h_gr32 byte_dest er0
478 test_gr_a5a5 1 ; Make sure other general regs not disturbed
485 ; 1010 0101 -> 1110 1001
486 cmp.b #0xe9, @byte_dest
490 mov.b #0xa5, @byte_dest
493 set_grs_a5a5 ; Fill all general regs with a fixed pattern
496 mov #byte_dest+1, er0
497 shar.b #2, @-er0 ; shift right arithmetic by two, predec
502 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
507 test_h_gr32 byte_dest er0
508 test_gr_a5a5 1 ; Make sure other general regs not disturbed
515 ; 1010 0101 -> 1110 1001
516 cmp.b #0xe9, @byte_dest
520 mov.b #0xa5, @byte_dest
523 set_grs_a5a5 ; Fill all general regs with a fixed pattern
526 mov #byte_dest-2, er0
527 shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
532 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
537 test_h_gr32 byte_dest-2 er0
538 test_gr_a5a5 1 ; Make sure other general regs not disturbed
545 ; 1010 0101 -> 1110 1001
546 cmp.b #0xe9, @byte_dest
550 mov.b #0xa5, @byte_dest
553 set_grs_a5a5 ; Fill all general regs with a fixed pattern
556 mov #byte_dest-44, er0
557 shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
563 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
568 test_h_gr32 byte_dest-44 er0
569 test_gr_a5a5 1 ; Make sure other general regs not disturbed
576 ; 1010 0101 -> 1110 1001
577 cmp.b #0xe9, @byte_dest
581 mov.b #0xa5, @byte_dest
584 set_grs_a5a5 ; Fill all general regs with a fixed pattern
587 mov #byte_dest-666, er0
588 shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
594 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
599 test_h_gr32 byte_dest-666 er0
600 test_gr_a5a5 1 ; Make sure other general regs not disturbed
607 ; 1010 0101 -> 1110 1001
608 cmp.b #0xe9, @byte_dest
612 mov.b #0xa5, @byte_dest
615 set_grs_a5a5 ; Fill all general regs with a fixed pattern
618 shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
623 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
628 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
636 ; 1010 0101 -> 1110 1001
637 cmp.b #0xe9, @byte_dest
641 mov.b #0xa5, @byte_dest
644 set_grs_a5a5 ; Fill all general regs with a fixed pattern
647 shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
652 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
657 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
665 ; 1010 0101 -> 1110 1001
666 cmp.b #0xe9, @byte_dest
670 mov.b #0xa5, @byte_dest
673 .if (sim_cpu) ; Not available in h8300 mode
675 set_grs_a5a5 ; Fill all general regs with a fixed pattern
678 shar.w r0 ; shift right arithmetic by one
681 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
685 test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
686 test_h_gr32 0xa5a5d2d2 er0
688 test_gr_a5a5 1 ; Make sure other general regs not disturbed
696 .if (sim_cpu == h8sx)
698 set_grs_a5a5 ; Fill all general regs with a fixed pattern
702 shar.w @er0 ; shift right arithmetic by one, indirect
706 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
711 test_h_gr32 word_dest er0
712 test_gr_a5a5 1 ; Make sure other general regs not disturbed
719 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
720 cmp.w #0xd2d2, @word_dest
724 mov.w #0xa5a5, @word_dest
727 set_grs_a5a5 ; Fill all general regs with a fixed pattern
731 shar.w @er0+ ; shift right arithmetic by one, postinc
736 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
741 test_h_gr32 word_dest+2 er0
742 test_gr_a5a5 1 ; Make sure other general regs not disturbed
749 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
750 cmp.w #0xd2d2, @word_dest
754 mov.w #0xa5a5, @word_dest
757 set_grs_a5a5 ; Fill all general regs with a fixed pattern
761 shar.w @er0- ; shift right arithmetic by one, postdec
766 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
771 test_h_gr32 word_dest-2 er0
772 test_gr_a5a5 1 ; Make sure other general regs not disturbed
779 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
780 cmp.w #0xd2d2, @word_dest
784 mov.w #0xa5a5, @word_dest
787 set_grs_a5a5 ; Fill all general regs with a fixed pattern
790 mov #word_dest-2, er0
791 shar.w @+er0 ; shift right arithmetic by one, preinc
796 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
801 test_h_gr32 word_dest er0
802 test_gr_a5a5 1 ; Make sure other general regs not disturbed
809 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
810 cmp.w #0xd2d2, @word_dest
814 mov.w #0xa5a5, @word_dest
817 set_grs_a5a5 ; Fill all general regs with a fixed pattern
820 mov #word_dest+2, er0
821 shar.w @-er0 ; shift right arithmetic by one, predec
826 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
831 test_h_gr32 word_dest er0
832 test_gr_a5a5 1 ; Make sure other general regs not disturbed
839 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
840 cmp.w #0xd2d2, @word_dest
844 mov.w #0xa5a5, @word_dest
847 set_grs_a5a5 ; Fill all general regs with a fixed pattern
850 mov #word_dest-4, er0
851 shar.w @(4:2, er0) ; shift right arithmetic by one, disp2
856 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
861 test_h_gr32 word_dest-4 er0
862 test_gr_a5a5 1 ; Make sure other general regs not disturbed
869 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
870 cmp.w #0xd2d2, @word_dest
874 mov.w #0xa5a5, @word_dest
877 set_grs_a5a5 ; Fill all general regs with a fixed pattern
880 mov #word_dest-44, er0
881 shar.w @(44:16, er0) ; shift right arithmetic by one, disp16
887 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
892 test_h_gr32 word_dest-44 er0
893 test_gr_a5a5 1 ; Make sure other general regs not disturbed
900 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
901 cmp.w #0xd2d2, @word_dest
905 mov.w #0xa5a5, @word_dest
908 set_grs_a5a5 ; Fill all general regs with a fixed pattern
911 mov #word_dest-666, er0
912 shar.w @(666:32, er0) ; shift right arithmetic by one, disp32
918 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
923 test_h_gr32 word_dest-666 er0
924 test_gr_a5a5 1 ; Make sure other general regs not disturbed
931 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
932 cmp.w #0xd2d2, @word_dest
936 mov.w #0xa5a5, @word_dest
939 set_grs_a5a5 ; Fill all general regs with a fixed pattern
942 shar.w @word_dest:16 ; shift right arithmetic by one, abs16
947 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
952 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
960 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
961 cmp.w #0xd2d2, @word_dest
965 mov.w #0xa5a5, @word_dest
968 set_grs_a5a5 ; Fill all general regs with a fixed pattern
971 shar.w @word_dest:32 ; shift right arithmetic by one, abs32
976 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
981 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
989 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
990 cmp.w #0xd2d2, @word_dest
994 mov.w #0xa5a5, @word_dest
998 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1001 shar.w #2, r0 ; shift right arithmetic by two
1004 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1009 test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1010 test_h_gr32 0xa5a5e969 er0
1011 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1019 .if (sim_cpu == h8sx)
1021 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1025 shar.w #2, @er0 ; shift right arithmetic by two, indirect
1029 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1034 test_h_gr32 word_dest er0
1035 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1042 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1043 cmp.w #0xe969, @word_dest
1047 mov.w #0xa5a5, @word_dest
1050 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1054 shar.w #2, @er0+ ; shift right arithmetic by two, postinc
1059 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1064 test_h_gr32 word_dest+2 er0
1065 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1072 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1073 cmp.w #0xe969, @word_dest
1077 mov.w #0xa5a5, @word_dest
1080 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1084 shar.w #2, @er0- ; shift right arithmetic by two, postdec
1089 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1094 test_h_gr32 word_dest-2 er0
1095 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1102 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1103 cmp.w #0xe969, @word_dest
1107 mov.w #0xa5a5, @word_dest
1110 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1113 mov #word_dest-2, er0
1114 shar.w #2, @+er0 ; shift right arithmetic by two, preinc
1119 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1124 test_h_gr32 word_dest er0
1125 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1132 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1133 cmp.w #0xe969, @word_dest
1137 mov.w #0xa5a5, @word_dest
1140 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1143 mov #word_dest+2, er0
1144 shar.w #2, @-er0 ; shift right arithmetic by two, predec
1149 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1154 test_h_gr32 word_dest er0
1155 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1162 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1163 cmp.w #0xe969, @word_dest
1167 mov.w #0xa5a5, @word_dest
1170 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1173 mov #word_dest-4, er0
1174 shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
1179 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1184 test_h_gr32 word_dest-4 er0
1185 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1192 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1193 cmp.w #0xe969, @word_dest
1197 mov.w #0xa5a5, @word_dest
1200 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1203 mov #word_dest-44, er0
1204 shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1210 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1215 test_h_gr32 word_dest-44 er0
1216 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1223 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1224 cmp.w #0xe969, @word_dest
1228 mov.w #0xa5a5, @word_dest
1231 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1234 mov #word_dest-666, er0
1235 shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1241 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1246 test_h_gr32 word_dest-666 er0
1247 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1254 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1255 cmp.w #0xe969, @word_dest
1259 mov.w #0xa5a5, @word_dest
1262 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1265 shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
1270 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1275 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1283 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1284 cmp.w #0xe969, @word_dest
1288 mov.w #0xa5a5, @word_dest
1291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1294 shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
1299 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1312 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1313 cmp.w #0xe969, @word_dest
1317 mov.w #0xa5a5, @word_dest
1321 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1324 shar.l er0 ; shift right arithmetic by one, register
1327 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1332 ; 1010 0101 1010 0101 1010 0101 1010 0101
1333 ; -> 1101 0010 1101 0010 1101 0010 1101 0010
1334 test_h_gr32 0xd2d2d2d2 er0
1336 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1344 .if (sim_cpu == h8sx)
1346 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1350 shar.l @er0 ; shift right arithmetic by one, indirect
1355 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1360 test_h_gr32 long_dest er0
1361 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1368 ; 1010 0101 1010 0101 1010 0101 1010 0101
1369 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1370 cmp.l #0xd2d2d2d2, @long_dest
1374 mov #0xa5a5a5a5, @long_dest
1377 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1381 shar.l @er0+ ; shift right arithmetic by one, postinc
1386 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1391 test_h_gr32 long_dest+4 er0
1392 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1399 ; 1010 0101 1010 0101 1010 0101 1010 0101
1400 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1401 cmp.l #0xd2d2d2d2, @long_dest
1405 mov #0xa5a5a5a5, @long_dest
1408 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1412 shar.l @er0- ; shift right arithmetic by one, postdec
1417 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1422 test_h_gr32 long_dest-4 er0
1423 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1430 ; 1010 0101 1010 0101 1010 0101 1010 0101
1431 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1432 cmp.l #0xd2d2d2d2, @long_dest
1436 mov #0xa5a5a5a5, @long_dest
1439 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1442 mov #long_dest-4, er0
1443 shar.l @+er0 ; shift right arithmetic by one, preinc
1448 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1453 test_h_gr32 long_dest er0
1454 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1461 ; 1010 0101 1010 0101 1010 0101 1010 0101
1462 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1463 cmp.l #0xd2d2d2d2, @long_dest
1467 mov #0xa5a5a5a5, @long_dest
1470 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1473 mov #long_dest+4, er0
1474 shar.l @-er0 ; shift right arithmetic by one, predec
1479 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1484 test_h_gr32 long_dest er0
1485 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1492 ; 1010 0101 1010 0101 1010 0101 1010 0101
1493 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1494 cmp.l #0xd2d2d2d2, @long_dest
1498 mov #0xa5a5a5a5, @long_dest
1501 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1504 mov #long_dest-8, er0
1505 shar.l @(8:2, er0) ; shift right arithmetic by one, disp2
1510 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1515 test_h_gr32 long_dest-8 er0
1516 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1523 ; 1010 0101 1010 0101 1010 0101 1010 0101
1524 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1525 cmp.l #0xd2d2d2d2, @long_dest
1529 mov #0xa5a5a5a5, @long_dest
1532 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1535 mov #long_dest-44, er0
1536 shar.l @(44:16, er0) ; shift right arithmetic by one, disp16
1542 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1547 test_h_gr32 long_dest-44 er0
1548 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1555 ; 1010 0101 1010 0101 1010 0101 1010 0101
1556 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1557 cmp.l #0xd2d2d2d2, @long_dest
1561 mov #0xa5a5a5a5, @long_dest
1564 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1567 mov #long_dest-666, er0
1568 shar.l @(666:32, er0) ; shift right arithmetic by one, disp32
1574 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1579 test_h_gr32 long_dest-666 er0
1580 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1587 ; 1010 0101 1010 0101 1010 0101 1010 0101
1588 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1589 cmp.l #0xd2d2d2d2, @long_dest
1593 mov #0xa5a5a5a5, @long_dest
1596 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1599 shar.l @long_dest:16 ; shift right arithmetic by one, abs16
1605 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1610 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1618 ; 1010 0101 1010 0101 1010 0101 1010 0101
1619 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1620 cmp.l #0xd2d2d2d2, @long_dest
1624 mov #0xa5a5a5a5, @long_dest
1627 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1630 shar.l @long_dest:32 ; shift right arithmetic by one, abs32
1636 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1641 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1649 ; 1010 0101 1010 0101 1010 0101 1010 0101
1650 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1651 cmp.l #0xd2d2d2d2, @long_dest
1655 mov #0xa5a5a5a5, @long_dest
1659 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1662 shar.l #2, er0 ; shift right arithmetic by two, register
1665 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1669 ; 1010 0101 1010 0101 1010 0101 1010 0101
1670 ; -> 1110 1001 0110 1001 0110 1001 0110 1001
1671 test_h_gr32 0xe9696969 er0
1673 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1681 .if (sim_cpu == h8sx)
1684 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1688 shar.l #2, @er0 ; shift right arithmetic by two, indirect
1693 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1698 test_h_gr32 long_dest er0
1699 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1706 ; 1010 0101 1010 0101 1010 0101 1010 0101
1707 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1708 cmp.l #0xe9696969, @long_dest
1712 mov #0xa5a5a5a5, @long_dest
1715 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1719 shar.l #2, @er0+ ; shift right arithmetic by two, postinc
1724 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1729 test_h_gr32 long_dest+4 er0
1730 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1737 ; 1010 0101 1010 0101 1010 0101 1010 0101
1738 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1739 cmp.l #0xe9696969, @long_dest
1743 mov #0xa5a5a5a5, @long_dest
1746 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1750 shar.l #2, @er0- ; shift right arithmetic by two, postdec
1755 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1760 test_h_gr32 long_dest-4 er0
1761 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1768 ; 1010 0101 1010 0101 1010 0101 1010 0101
1769 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1770 cmp.l #0xe9696969, @long_dest
1774 mov #0xa5a5a5a5, @long_dest
1777 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1780 mov #long_dest-4, er0
1781 shar.l #2, @+er0 ; shift right arithmetic by two, preinc
1786 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1791 test_h_gr32 long_dest er0
1792 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1799 ; 1010 0101 1010 0101 1010 0101 1010 0101
1800 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1801 cmp.l #0xe9696969, @long_dest
1805 mov #0xa5a5a5a5, @long_dest
1808 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1811 mov #long_dest+4, er0
1812 shar.l #2, @-er0 ; shift right arithmetic by two, predec
1817 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1822 test_h_gr32 long_dest er0
1823 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1830 ; 1010 0101 1010 0101 1010 0101 1010 0101
1831 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1832 cmp.l #0xe9696969, @long_dest
1836 mov #0xa5a5a5a5, @long_dest
1839 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1842 mov #long_dest-8, er0
1843 shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
1848 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1853 test_h_gr32 long_dest-8 er0
1854 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1861 ; 1010 0101 1010 0101 1010 0101 1010 0101
1862 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1863 cmp.l #0xe9696969, @long_dest
1867 mov #0xa5a5a5a5, @long_dest
1870 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1873 mov #long_dest-44, er0
1874 shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1880 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1885 test_h_gr32 long_dest-44 er0
1886 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1893 ; 1010 0101 1010 0101 1010 0101 1010 0101
1894 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1895 cmp.l #0xe9696969, @long_dest
1899 mov #0xa5a5a5a5, @long_dest
1902 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1905 mov #long_dest-666, er0
1906 shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1912 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1917 test_h_gr32 long_dest-666 er0
1918 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1925 ; 1010 0101 1010 0101 1010 0101 1010 0101
1926 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1927 cmp.l #0xe9696969, @long_dest
1931 mov #0xa5a5a5a5, @long_dest
1934 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1937 shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
1943 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1948 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1956 ; 1010 0101 1010 0101 1010 0101 1010 0101
1957 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1958 cmp.l #0xe9696969, @long_dest
1962 mov #0xa5a5a5a5, @long_dest
1965 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1968 shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
1974 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1979 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1987 ; 1010 0101 1010 0101 1010 0101 1010 0101
1988 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1989 cmp.l #0xe9696969, @long_dest
1993 mov #0xa5a5a5a5, @long_dest