1 # Hitachi H8 testcase 'rotr'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
18 word_dest: .word 0xa5a5
20 long_dest: .long 0xa5a5a5a5
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
28 rotr.b r0l ; shift right arithmetic by one
30 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
35 test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
37 test_h_gr32 0xa5a5a5d2 er0
39 test_gr_a5a5 1 ; Make sure other general regs not disturbed
49 set_grs_a5a5 ; Fill all general regs with a fixed pattern
53 rotr.b @er0 ; shift right arithmetic by one, indirect
55 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
60 test_h_gr32 byte_dest er0
61 test_gr_a5a5 1 ; Make sure other general regs not disturbed
68 ; 1010 0101 -> 1101 0010
69 cmp.b #0xd2, @byte_dest
73 mov.b #0xa5, @byte_dest
76 set_grs_a5a5 ; Fill all general regs with a fixed pattern
80 rotr.b @er0+ ; shift right arithmetic by one, postinc
82 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
87 test_h_gr32 byte_dest+1 er0
88 test_gr_a5a5 1 ; Make sure other general regs not disturbed
95 ; 1010 0101 -> 1101 0010
96 cmp.b #0xd2, @byte_dest
100 mov.b #0xa5, @byte_dest
103 set_grs_a5a5 ; Fill all general regs with a fixed pattern
107 rotr.b @er0- ; shift right arithmetic by one, postdec
109 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
114 test_h_gr32 byte_dest-1 er0
115 test_gr_a5a5 1 ; Make sure other general regs not disturbed
122 ; 1010 0101 -> 1101 0010
123 cmp.b #0xd2, @byte_dest
127 mov.b #0xa5, @byte_dest
130 set_grs_a5a5 ; Fill all general regs with a fixed pattern
133 mov #byte_dest-1, er0
134 rotr.b @+er0 ; shift right arithmetic by one, preinc
136 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
141 test_h_gr32 byte_dest er0
142 test_gr_a5a5 1 ; Make sure other general regs not disturbed
149 ; 1010 0101 -> 1101 0010
150 cmp.b #0xd2, @byte_dest
154 mov.b #0xa5, @byte_dest
157 set_grs_a5a5 ; Fill all general regs with a fixed pattern
160 mov #byte_dest+1, er0
161 rotr.b @-er0 ; shift right arithmetic by one, predec
163 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
168 test_h_gr32 byte_dest er0
169 test_gr_a5a5 1 ; Make sure other general regs not disturbed
176 ; 1010 0101 -> 1101 0010
177 cmp.b #0xd2, @byte_dest
181 mov.b #0xa5, @byte_dest
184 set_grs_a5a5 ; Fill all general regs with a fixed pattern
187 mov #byte_dest-2, er0
188 rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2
190 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
195 test_h_gr32 byte_dest-2 er0
196 test_gr_a5a5 1 ; Make sure other general regs not disturbed
203 ; 1010 0101 -> 1101 0010
204 cmp.b #0xd2, @byte_dest
208 mov.b #0xa5, @byte_dest
211 set_grs_a5a5 ; Fill all general regs with a fixed pattern
214 mov #byte_dest-44, er0
215 rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16
217 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
222 test_h_gr32 byte_dest-44 er0
223 test_gr_a5a5 1 ; Make sure other general regs not disturbed
230 ; 1010 0101 -> 1101 0010
231 cmp.b #0xd2, @byte_dest
235 mov.b #0xa5, @byte_dest
238 set_grs_a5a5 ; Fill all general regs with a fixed pattern
241 mov #byte_dest-666, er0
242 rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32
244 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
249 test_h_gr32 byte_dest-666 er0
250 test_gr_a5a5 1 ; Make sure other general regs not disturbed
257 ; 1010 0101 -> 1101 0010
258 cmp.b #0xd2, @byte_dest
262 mov.b #0xa5, @byte_dest
265 set_grs_a5a5 ; Fill all general regs with a fixed pattern
268 rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16
270 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
275 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
283 ; 1010 0101 -> 1101 0010
284 cmp.b #0xd2, @byte_dest
288 mov.b #0xa5, @byte_dest
291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
294 rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32
296 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
301 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
309 ; 1010 0101 -> 1101 0010
310 cmp.b #0xd2, @byte_dest
314 mov.b #0xa5, @byte_dest
318 set_grs_a5a5 ; Fill all general regs with a fixed pattern
321 rotr.b #2, r0l ; shift right arithmetic by two
323 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
327 test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001
329 test_h_gr32 0xa5a5a569 er0
331 test_gr_a5a5 1 ; Make sure other general regs not disturbed
339 .if (sim_cpu == h8sx)
341 set_grs_a5a5 ; Fill all general regs with a fixed pattern
345 rotr.b #2, @er0 ; shift right arithmetic by two, indirect
347 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
352 test_h_gr32 byte_dest er0
353 test_gr_a5a5 1 ; Make sure other general regs not disturbed
360 ; 1010 0101 -> 0110 1001
361 cmp.b #0x69, @byte_dest
365 mov.b #0xa5, @byte_dest
368 set_grs_a5a5 ; Fill all general regs with a fixed pattern
372 rotr.b #2, @er0+ ; shift right arithmetic by two, postinc
374 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
379 test_h_gr32 byte_dest+1 er0
380 test_gr_a5a5 1 ; Make sure other general regs not disturbed
387 ; 1010 0101 -> 0110 1001
388 cmp.b #0x69, @byte_dest
392 mov.b #0xa5, @byte_dest
395 set_grs_a5a5 ; Fill all general regs with a fixed pattern
399 rotr.b #2, @er0- ; shift right arithmetic by two, postdec
401 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
406 test_h_gr32 byte_dest-1 er0
407 test_gr_a5a5 1 ; Make sure other general regs not disturbed
414 ; 1010 0101 -> 0110 1001
415 cmp.b #0x69, @byte_dest
419 mov.b #0xa5, @byte_dest
422 set_grs_a5a5 ; Fill all general regs with a fixed pattern
425 mov #byte_dest-1, er0
426 rotr.b #2, @+er0 ; shift right arithmetic by two, preinc
428 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
433 test_h_gr32 byte_dest er0
434 test_gr_a5a5 1 ; Make sure other general regs not disturbed
441 ; 1010 0101 -> 0110 1001
442 cmp.b #0x69, @byte_dest
446 mov.b #0xa5, @byte_dest
449 set_grs_a5a5 ; Fill all general regs with a fixed pattern
452 mov #byte_dest+1, er0
453 rotr.b #2, @-er0 ; shift right arithmetic by two, predec
455 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
460 test_h_gr32 byte_dest er0
461 test_gr_a5a5 1 ; Make sure other general regs not disturbed
468 ; 1010 0101 -> 0110 1001
469 cmp.b #0x69, @byte_dest
473 mov.b #0xa5, @byte_dest
476 set_grs_a5a5 ; Fill all general regs with a fixed pattern
479 mov #byte_dest-2, er0
480 rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
482 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
487 test_h_gr32 byte_dest-2 er0
488 test_gr_a5a5 1 ; Make sure other general regs not disturbed
495 ; 1010 0101 -> 0110 1001
496 cmp.b #0x69, @byte_dest
500 mov.b #0xa5, @byte_dest
503 set_grs_a5a5 ; Fill all general regs with a fixed pattern
506 mov #byte_dest-44, er0
507 rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
509 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
514 test_h_gr32 byte_dest-44 er0
515 test_gr_a5a5 1 ; Make sure other general regs not disturbed
522 ; 1010 0101 -> 0110 1001
523 cmp.b #0x69, @byte_dest
527 mov.b #0xa5, @byte_dest
530 set_grs_a5a5 ; Fill all general regs with a fixed pattern
533 mov #byte_dest-666, er0
534 rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
536 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
541 test_h_gr32 byte_dest-666 er0
542 test_gr_a5a5 1 ; Make sure other general regs not disturbed
549 ; 1010 0101 -> 0110 1001
550 cmp.b #0x69, @byte_dest
554 mov.b #0xa5, @byte_dest
557 set_grs_a5a5 ; Fill all general regs with a fixed pattern
560 rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
562 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
567 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
575 ; 1010 0101 -> 0110 1001
576 cmp.b #0x69, @byte_dest
580 mov.b #0xa5, @byte_dest
583 set_grs_a5a5 ; Fill all general regs with a fixed pattern
586 rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
588 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
593 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
601 ; 1010 0101 -> 0110 1001
602 cmp.b #0x69, @byte_dest
606 mov.b #0xa5, @byte_dest
609 .if (sim_cpu) ; Not available in h8300 mode
611 set_grs_a5a5 ; Fill all general regs with a fixed pattern
614 rotr.w r0 ; shift right arithmetic by one
616 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
620 test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
621 test_h_gr32 0xa5a5d2d2 er0
623 test_gr_a5a5 1 ; Make sure other general regs not disturbed
631 .if (sim_cpu == h8sx)
633 set_grs_a5a5 ; Fill all general regs with a fixed pattern
637 rotr.w @er0 ; shift right arithmetic by one, indirect
639 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
644 test_h_gr32 word_dest er0
645 test_gr_a5a5 1 ; Make sure other general regs not disturbed
652 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
653 cmp.w #0xd2d2, @word_dest
657 mov.w #0xa5a5, @word_dest
660 set_grs_a5a5 ; Fill all general regs with a fixed pattern
664 rotr.w @er0+ ; shift right arithmetic by one, postinc
666 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
671 test_h_gr32 word_dest+2 er0
672 test_gr_a5a5 1 ; Make sure other general regs not disturbed
679 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
680 cmp.w #0xd2d2, @word_dest
684 mov.w #0xa5a5, @word_dest
687 set_grs_a5a5 ; Fill all general regs with a fixed pattern
691 rotr.w @er0- ; shift right arithmetic by one, postdec
693 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
698 test_h_gr32 word_dest-2 er0
699 test_gr_a5a5 1 ; Make sure other general regs not disturbed
706 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
707 cmp.w #0xd2d2, @word_dest
711 mov.w #0xa5a5, @word_dest
714 set_grs_a5a5 ; Fill all general regs with a fixed pattern
717 mov #word_dest-2, er0
718 rotr.w @+er0 ; shift right arithmetic by one, preinc
720 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
725 test_h_gr32 word_dest er0
726 test_gr_a5a5 1 ; Make sure other general regs not disturbed
733 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
734 cmp.w #0xd2d2, @word_dest
738 mov.w #0xa5a5, @word_dest
741 set_grs_a5a5 ; Fill all general regs with a fixed pattern
744 mov #word_dest+2, er0
745 rotr.w @-er0 ; shift right arithmetic by one, predec
747 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
752 test_h_gr32 word_dest er0
753 test_gr_a5a5 1 ; Make sure other general regs not disturbed
760 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
761 cmp.w #0xd2d2, @word_dest
765 mov.w #0xa5a5, @word_dest
768 set_grs_a5a5 ; Fill all general regs with a fixed pattern
771 mov #word_dest-4, er0
772 rotr.w @(4:2, er0) ; shift right arithmetic by one, disp2
774 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
779 test_h_gr32 word_dest-4 er0
780 test_gr_a5a5 1 ; Make sure other general regs not disturbed
787 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
788 cmp.w #0xd2d2, @word_dest
792 mov.w #0xa5a5, @word_dest
795 set_grs_a5a5 ; Fill all general regs with a fixed pattern
798 mov #word_dest-44, er0
799 rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16
801 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
806 test_h_gr32 word_dest-44 er0
807 test_gr_a5a5 1 ; Make sure other general regs not disturbed
814 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
815 cmp.w #0xd2d2, @word_dest
819 mov.w #0xa5a5, @word_dest
822 set_grs_a5a5 ; Fill all general regs with a fixed pattern
825 mov #word_dest-666, er0
826 rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32
828 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
833 test_h_gr32 word_dest-666 er0
834 test_gr_a5a5 1 ; Make sure other general regs not disturbed
841 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
842 cmp.w #0xd2d2, @word_dest
846 mov.w #0xa5a5, @word_dest
849 set_grs_a5a5 ; Fill all general regs with a fixed pattern
852 rotr.w @word_dest:16 ; shift right arithmetic by one, abs16
854 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
859 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
867 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
868 cmp.w #0xd2d2, @word_dest
872 mov.w #0xa5a5, @word_dest
875 set_grs_a5a5 ; Fill all general regs with a fixed pattern
878 rotr.w @word_dest:32 ; shift right arithmetic by one, abs32
880 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
885 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
893 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
894 cmp.w #0xd2d2, @word_dest
898 mov.w #0xa5a5, @word_dest
902 set_grs_a5a5 ; Fill all general regs with a fixed pattern
905 rotr.w #2, r0 ; shift right arithmetic by two
907 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
912 test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
913 test_h_gr32 0xa5a56969 er0
914 test_gr_a5a5 1 ; Make sure other general regs not disturbed
922 .if (sim_cpu == h8sx)
924 set_grs_a5a5 ; Fill all general regs with a fixed pattern
928 rotr.w #2, @er0 ; shift right arithmetic by two, indirect
930 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
935 test_h_gr32 word_dest er0
936 test_gr_a5a5 1 ; Make sure other general regs not disturbed
943 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
944 cmp.w #0x6969, @word_dest
948 mov.w #0xa5a5, @word_dest
951 set_grs_a5a5 ; Fill all general regs with a fixed pattern
955 rotr.w #2, @er0+ ; shift right arithmetic by two, postinc
957 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
962 test_h_gr32 word_dest+2 er0
963 test_gr_a5a5 1 ; Make sure other general regs not disturbed
970 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
971 cmp.w #0x6969, @word_dest
975 mov.w #0xa5a5, @word_dest
978 set_grs_a5a5 ; Fill all general regs with a fixed pattern
982 rotr.w #2, @er0- ; shift right arithmetic by two, postdec
984 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
989 test_h_gr32 word_dest-2 er0
990 test_gr_a5a5 1 ; Make sure other general regs not disturbed
997 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
998 cmp.w #0x6969, @word_dest
1002 mov.w #0xa5a5, @word_dest
1005 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1008 mov #word_dest-2, er0
1009 rotr.w #2, @+er0 ; shift right arithmetic by two, preinc
1011 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1016 test_h_gr32 word_dest er0
1017 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1024 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1025 cmp.w #0x6969, @word_dest
1029 mov.w #0xa5a5, @word_dest
1032 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1035 mov #word_dest+2, er0
1036 rotr.w #2, @-er0 ; shift right arithmetic by two, predec
1038 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1043 test_h_gr32 word_dest er0
1044 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1051 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1052 cmp.w #0x6969, @word_dest
1056 mov.w #0xa5a5, @word_dest
1059 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1062 mov #word_dest-4, er0
1063 rotr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
1065 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1070 test_h_gr32 word_dest-4 er0
1071 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1078 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1079 cmp.w #0x6969, @word_dest
1083 mov.w #0xa5a5, @word_dest
1086 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1089 mov #word_dest-44, er0
1090 rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1092 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1097 test_h_gr32 word_dest-44 er0
1098 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1105 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1106 cmp.w #0x6969, @word_dest
1110 mov.w #0xa5a5, @word_dest
1113 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1116 mov #word_dest-666, er0
1117 rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1119 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1124 test_h_gr32 word_dest-666 er0
1125 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1132 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1133 cmp.w #0x6969, @word_dest
1137 mov.w #0xa5a5, @word_dest
1140 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1143 rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
1145 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1150 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1158 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1159 cmp.w #0x6969, @word_dest
1163 mov.w #0xa5a5, @word_dest
1166 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1169 rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
1171 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1176 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1184 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1185 cmp.w #0x6969, @word_dest
1189 mov.w #0xa5a5, @word_dest
1193 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1196 rotr.l er0 ; shift right arithmetic by one, register
1198 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1203 ; 1010 0101 1010 0101 1010 0101 1010 0101
1204 ; -> 1101 0010 1101 0010 1101 0010 1101 0010
1205 test_h_gr32 0xd2d2d2d2 er0
1207 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1215 .if (sim_cpu == h8sx)
1217 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1221 rotr.l @er0 ; shift right arithmetic by one, indirect
1223 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1228 test_h_gr32 long_dest er0
1229 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1236 ; 1010 0101 1010 0101 1010 0101 1010 0101
1237 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1238 cmp.l #0xd2d2d2d2, @long_dest
1242 mov #0xa5a5a5a5, @long_dest
1245 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1249 rotr.l @er0+ ; shift right arithmetic by one, postinc
1251 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1256 test_h_gr32 long_dest+4 er0
1257 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1264 ; 1010 0101 1010 0101 1010 0101 1010 0101
1265 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1266 cmp.l #0xd2d2d2d2, @long_dest
1270 mov #0xa5a5a5a5, @long_dest
1273 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1277 rotr.l @er0- ; shift right arithmetic by one, postdec
1279 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1284 test_h_gr32 long_dest-4 er0
1285 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1292 ; 1010 0101 1010 0101 1010 0101 1010 0101
1293 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1294 cmp.l #0xd2d2d2d2, @long_dest
1298 mov #0xa5a5a5a5, @long_dest
1301 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1304 mov #long_dest-4, er0
1305 rotr.l @+er0 ; shift right arithmetic by one, preinc
1307 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1312 test_h_gr32 long_dest er0
1313 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1320 ; 1010 0101 1010 0101 1010 0101 1010 0101
1321 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1322 cmp.l #0xd2d2d2d2, @long_dest
1326 mov #0xa5a5a5a5, @long_dest
1329 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1332 mov #long_dest+4, er0
1333 rotr.l @-er0 ; shift right arithmetic by one, predec
1335 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1340 test_h_gr32 long_dest er0
1341 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1348 ; 1010 0101 1010 0101 1010 0101 1010 0101
1349 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1350 cmp.l #0xd2d2d2d2, @long_dest
1354 mov #0xa5a5a5a5, @long_dest
1357 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1360 mov #long_dest-8, er0
1361 rotr.l @(8:2, er0) ; shift right arithmetic by one, disp2
1363 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1368 test_h_gr32 long_dest-8 er0
1369 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1376 ; 1010 0101 1010 0101 1010 0101 1010 0101
1377 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1378 cmp.l #0xd2d2d2d2, @long_dest
1382 mov #0xa5a5a5a5, @long_dest
1385 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1388 mov #long_dest-44, er0
1389 rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16
1391 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1396 test_h_gr32 long_dest-44 er0
1397 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1404 ; 1010 0101 1010 0101 1010 0101 1010 0101
1405 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1406 cmp.l #0xd2d2d2d2, @long_dest
1410 mov #0xa5a5a5a5, @long_dest
1413 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1416 mov #long_dest-666, er0
1417 rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32
1419 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1424 test_h_gr32 long_dest-666 er0
1425 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1432 ; 1010 0101 1010 0101 1010 0101 1010 0101
1433 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1434 cmp.l #0xd2d2d2d2, @long_dest
1438 mov #0xa5a5a5a5, @long_dest
1441 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1444 rotr.l @long_dest:16 ; shift right arithmetic by one, abs16
1446 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1451 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1459 ; 1010 0101 1010 0101 1010 0101 1010 0101
1460 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1461 cmp.l #0xd2d2d2d2, @long_dest
1465 mov #0xa5a5a5a5, @long_dest
1468 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1471 rotr.l @long_dest:32 ; shift right arithmetic by one, abs32
1473 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1478 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1486 ; 1010 0101 1010 0101 1010 0101 1010 0101
1487 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1488 cmp.l #0xd2d2d2d2, @long_dest
1492 mov #0xa5a5a5a5, @long_dest
1496 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1499 rotr.l #2, er0 ; shift right arithmetic by two, register
1501 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1505 ; 1010 0101 1010 0101 1010 0101 1010 0101
1506 ; -> 0110 1001 0110 1001 0110 1001 0110 1001
1507 test_h_gr32 0x69696969 er0
1509 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1517 .if (sim_cpu == h8sx)
1520 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1524 rotr.l #2, @er0 ; shift right arithmetic by two, indirect
1526 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1531 test_h_gr32 long_dest er0
1532 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1539 ; 1010 0101 1010 0101 1010 0101 1010 0101
1540 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1541 cmp.l #0x69696969, @long_dest
1545 mov #0xa5a5a5a5, @long_dest
1548 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1552 rotr.l #2, @er0+ ; shift right arithmetic by two, postinc
1554 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1559 test_h_gr32 long_dest+4 er0
1560 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1567 ; 1010 0101 1010 0101 1010 0101 1010 0101
1568 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1569 cmp.l #0x69696969, @long_dest
1573 mov #0xa5a5a5a5, @long_dest
1576 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1580 rotr.l #2, @er0- ; shift right arithmetic by two, postdec
1582 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1587 test_h_gr32 long_dest-4 er0
1588 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1595 ; 1010 0101 1010 0101 1010 0101 1010 0101
1596 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1597 cmp.l #0x69696969, @long_dest
1601 mov #0xa5a5a5a5, @long_dest
1604 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1607 mov #long_dest-4, er0
1608 rotr.l #2, @+er0 ; shift right arithmetic by two, preinc
1610 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1615 test_h_gr32 long_dest er0
1616 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1623 ; 1010 0101 1010 0101 1010 0101 1010 0101
1624 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1625 cmp.l #0x69696969, @long_dest
1629 mov #0xa5a5a5a5, @long_dest
1632 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1635 mov #long_dest+4, er0
1636 rotr.l #2, @-er0 ; shift right arithmetic by two, predec
1638 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1643 test_h_gr32 long_dest er0
1644 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1651 ; 1010 0101 1010 0101 1010 0101 1010 0101
1652 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1653 cmp.l #0x69696969, @long_dest
1657 mov #0xa5a5a5a5, @long_dest
1660 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1663 mov #long_dest-8, er0
1664 rotr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
1666 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1671 test_h_gr32 long_dest-8 er0
1672 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1679 ; 1010 0101 1010 0101 1010 0101 1010 0101
1680 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1681 cmp.l #0x69696969, @long_dest
1685 mov #0xa5a5a5a5, @long_dest
1688 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1691 mov #long_dest-44, er0
1692 rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1694 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1699 test_h_gr32 long_dest-44 er0
1700 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1707 ; 1010 0101 1010 0101 1010 0101 1010 0101
1708 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1709 cmp.l #0x69696969, @long_dest
1713 mov #0xa5a5a5a5, @long_dest
1716 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1719 mov #long_dest-666, er0
1720 rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1722 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1727 test_h_gr32 long_dest-666 er0
1728 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1735 ; 1010 0101 1010 0101 1010 0101 1010 0101
1736 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1737 cmp.l #0x69696969, @long_dest
1741 mov #0xa5a5a5a5, @long_dest
1744 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1747 rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
1749 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1754 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1762 ; 1010 0101 1010 0101 1010 0101 1010 0101
1763 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1764 cmp.l #0x69696969, @long_dest
1768 mov #0xa5a5a5a5, @long_dest
1771 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1774 rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
1776 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
1781 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1789 ; 1010 0101 1010 0101 1010 0101 1010 0101
1790 ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1791 cmp.l #0x69696969, @long_dest
1795 mov #0xa5a5a5a5, @long_dest