1 # Hitachi H8 testcase 'mac'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
43 ;; Now see if the mac is actually clear...
63 ;; neg and zero are undefined
64 test_h_gr32 0xa5a5a5a5 er2
72 ;; neg and zero are undefined
73 test_h_gr32 0x0001a5 er2
75 test_gr_a5a5 0 ; Make sure other general regs not disturbed
96 test_h_gr32 0xa5a5a5a5 er0
97 test_h_gr32 src1+2 er1
98 test_h_gr32 src2+2 er2
99 test_h_gr32 0xa5a5a5a5 er3
100 test_h_gr32 0xa5a5a5a5 er4
101 test_h_gr32 0xa5a5a5a5 er5
102 test_h_gr32 0xa5a5a5a5 er6
103 test_h_gr32 0xa5a5a5a5 er7
118 ;; Use same reg for src and dst. Should be incremented twice,
119 ;; and fetch values from consecutive locations.
129 mac @er1+, @er1+ ; same register for src and dst
132 test_h_gr32 0xa5a5a5a5 er0
133 test_h_gr32 src1+4 er1
134 test_h_gr32 0xa5a50004 er2
135 test_h_gr32 0xa5a5a5a5 er3
136 test_h_gr32 0xa5a5a5a5 er4
137 test_h_gr32 0xa5a5a5a5 er5
138 test_h_gr32 0xa5a5a5a5 er6
139 test_h_gr32 0xa5a5a5a5 er7
166 test_h_gr32 0xa5a5a5a5 er0
167 test_h_gr32 src1+2 er1
168 test_h_gr32 src2+2 er2
169 test_h_gr32 0xa5a5a5a5 er3
170 test_h_gr32 0xa5a5a5a5 er4
171 test_h_gr32 0xa5a5a5a5 er5
172 test_h_gr32 0xa5a5a5a5 er6
173 test_h_gr32 0xa5a5a5a5 er7
176 test_zero_set ; zero flag is set
179 test_h_gr32 0 er0 ; result is zero
200 test_h_gr32 0xa5a5a5a5 er0
201 test_h_gr32 src1+2 er1
202 test_h_gr32 src2+2 er2
203 test_h_gr32 0xa5a5a5a5 er3
204 test_h_gr32 0xa5a5a5a5 er4
205 test_h_gr32 0xa5a5a5a5 er5
206 test_h_gr32 0xa5a5a5a5 er6
207 test_h_gr32 0xa5a5a5a5 er7
211 test_neg_set ; neg flag is set
213 test_h_gr32 -4 er0 ; result is negative
219 test_h_gr32 -1 er0 ; negative sign extend
222 ;; Use same reg for src and dst, pointing to an array of shorts
228 mac @er1+, @er1+ ; same register for src and dst
229 mac @er1+, @er1+ ; repeat 8 times
238 test_h_gr32 0xa5a5a5a5 er0
239 test_h_gr32 array+32 er1
240 test_h_gr32 0xa5a5a5a5 er2
241 test_h_gr32 0xa5a5a5a5 er3
242 test_h_gr32 0xa5a5a5a5 er4
243 test_h_gr32 0xa5a5a5a5 er5
244 test_h_gr32 0xa5a5a5a5 er6
245 test_h_gr32 0xa5a5a5a5 er7
251 test_h_gr32 0xfff80008 er0
257 test_h_gr32 1 er0 ; result is greater than 32 bits