1 # Hitachi H8 testcase 'jmp'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
21 set_grs_a5a5 ; Fill all general regs with a fixed pattern
22 mov.l #.Ltgt_8:32, @0x20
24 ;; jmp @@aa:8 ; 8-bit displacement
30 test_gr_a5a5 0 ; Make sure other general regs not disturbed
40 mov.l #vector_area, er0
43 mov.l #.Ltgt_7:32, @vector_area+0x300
52 test_h_gr32 vector_area, er0
57 set_grs_a5a5 ; Fill all general regs with a fixed pattern
60 ;; jmp @aa:24 ; 24-bit address
66 test_gr_a5a5 0 ; Make sure other general regs not disturbed
75 .if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx
77 set_grs_a5a5 ; Fill all general regs with a fixed pattern
80 ;; jmp @ern ; register indirect
87 test_gr_a5a5 0 ; Make sure other general regs not disturbed
92 test_h_gr32 .Ltgt_reg er5
99 set_grs_a5a5 ; Fill all general regs with a fixed pattern
102 ;; jmp @aa:32 ; 32-bit address
103 ; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing
110 test_gr_a5a5 0 ; Make sure other general regs not disturbed