1 # Hitachi H8 testcase 'and.b'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
13 # Instructions tested:
14 # and.b #xx:8, rd ; e rd xxxxxxxx
15 # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx
16 # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
17 # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
18 # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
19 # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
20 # and.b rs, rd ; 1 6 rs rd
21 # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????
22 # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs
23 # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs
24 # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs
25 # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs
27 # andc #xx:8, ccr ; 0 6 xxxxxxxx
28 # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx
41 set_grs_a5a5 ; Fill all general regs with a fixed pattern
45 and.b #0xaa, r0l ; Immediate 8-bit operand
47 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
48 test_h_gr16 0xa5a0 r0 ; and result: a5 & aa
49 .if (sim_cpu) ; non-zero means h8300h, s, or sx
50 test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa
52 test_gr_a5a5 1 ; Make sure other general regs not disturbed
62 set_grs_a5a5 ; Fill all general regs with a fixed pattern
67 and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
71 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
76 test_h_gr32 byte_dest, er0 ; er0 still contains address
77 test_gr_a5a5 1 ; Make sure other general regs not disturbed
85 ;; Now check the result of the and to memory.
98 set_grs_a5a5 ; Fill all general regs with a fixed pattern
103 and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
108 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
113 test_h_gr32 post_byte, er0 ; er0 contains address plus one
114 test_gr_a5a5 1 ; Make sure other general regs not disturbed
122 ;; Now check the result of the and to memory.
124 mov.b @byte_dest, r0l
130 and_b_imm8_rdpostdec:
135 set_grs_a5a5 ; Fill all general regs with a fixed pattern
140 and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
145 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
150 test_h_gr32 pre_byte, er0 ; er0 contains address minus one
151 test_gr_a5a5 1 ; Make sure other general regs not disturbed
159 ;; Now check the result of the and to memory.
161 mov.b @byte_dest, r0l
172 set_grs_a5a5 ; Fill all general regs with a fixed pattern
177 and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
182 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
187 test_h_gr32 byte_dest, er0 ; er0 contains destination address
188 test_gr_a5a5 1 ; Make sure other general regs not disturbed
196 ;; Now check the result of the and to memory.
198 mov.b @byte_dest, r0l
209 set_grs_a5a5 ; Fill all general regs with a fixed pattern
214 and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
219 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
224 test_h_gr32 byte_dest, er0 ; er0 contains destination address
225 test_gr_a5a5 1 ; Make sure other general regs not disturbed
233 ;; Now check the result of the and to memory.
235 mov.b @byte_dest, r0l
244 set_grs_a5a5 ; Fill all general regs with a fixed pattern
249 and.b r0h, r0l ; Register operand
251 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
252 test_h_gr16 0xaaa0 r0 ; and result: a5 & aa
253 .if (sim_cpu) ; non-zero means h8300h, s, or sx
254 test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa
256 test_gr_a5a5 1 ; Make sure other general regs not disturbed
264 .if (sim_cpu == h8sx)
270 set_grs_a5a5 ; Fill all general regs with a fixed pattern
273 ;; and.b rs8,@eRd ; And to register indirect
276 and.b r1l, @er0 ; reg8 src, reg indirect dest
280 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
285 test_h_gr32 byte_dest er0 ; er0 still contains address
286 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
288 test_gr_a5a5 2 ; Make sure other general regs not disturbed
295 ;; Now check the result of the and to memory.
297 mov.b @byte_dest, r0l
303 and_b_reg8_rdpostinc:
308 set_grs_a5a5 ; Fill all general regs with a fixed pattern
311 ;; and.b rs8,@eRd+ ; And to register post-incr
314 and.b r1l, @er0+ ; reg8 src, reg post-incr dest
318 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
323 test_h_gr32 post_byte er0 ; er0 contains address plus one
324 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
326 test_gr_a5a5 2 ; Make sure other general regs not disturbed
333 ;; Now check the result of the and to memory.
335 mov.b @byte_dest, r0l
341 and_b_reg8_rdpostdec:
346 set_grs_a5a5 ; Fill all general regs with a fixed pattern
349 ;; and.b rs8,@eRd- ; And to register post-decr
352 and.b r1l, @er0- ; reg8 src, reg post-decr dest
356 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
361 test_h_gr32 pre_byte er0 ; er0 contains address minus one
362 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
364 test_gr_a5a5 2 ; Make sure other general regs not disturbed
371 ;; Now check the result of the and to memory.
373 mov.b @byte_dest, r0l
384 set_grs_a5a5 ; Fill all general regs with a fixed pattern
387 ;; and.b rs8,@+eRd ; And to register post-incr
390 and.b r1l, @+er0 ; reg8 src, reg post-incr dest
394 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
399 test_h_gr32 byte_dest er0 ; er0 contains destination address
400 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
402 test_gr_a5a5 2 ; Make sure other general regs not disturbed
409 ;; Now check the result of the and to memory.
411 mov.b @byte_dest, r0l
422 set_grs_a5a5 ; Fill all general regs with a fixed pattern
425 ;; and.b rs8,@-eRd ; And to register post-decr
428 and.b r1l, @-er0 ; reg8 src, reg post-decr dest
432 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
437 test_h_gr32 byte_dest er0 ; er0 contains destination address
438 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
440 test_gr_a5a5 2 ; Make sure other general regs not disturbed
447 ;; Now check the result of the and to memory.
449 mov.b @byte_dest, r0l
457 set_grs_a5a5 ; Fill all general regs with a fixed pattern
464 andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)
468 andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)
472 andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)
476 andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)
479 test_gr_a5a5 0 ; Make sure other general regs not disturbed
488 .if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
490 set_grs_a5a5 ; Fill all general regs with a fixed pattern
515 test_h_gr32 0xa5a5a500 er0
523 .endif ; not h8300 or h8300h