sim/testsuite/sim/frv/tinv.cgs

   1 # frv testcase for tinv $ICCi_2,$GRi,$s12
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tinv
   9 tinv:
  10         and_spr_immed   -4081,tbr               ; clear tbr.tt
  11         set_gr_spr      tbr,gr7
  12         inc_gr_immed    2112,gr7                ; address of exception handler
  13         set_bctrlr_0_0  gr7     ; bctrlr 0,0
  14
  15         set_spr_immed   128,lcr
  16         set_gr_immed    0,gr7
  17
  18         set_psr_et      1
  19         set_spr_addr    ok0,lr
  20         set_icc         0x0 0
  21         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  22         fail
  23 ok0:
  24         set_psr_et      1
  25         set_spr_addr    ok1,lr
  26         set_icc         0x1 0
  27         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  28         fail
  29 ok1:
  30         set_spr_addr    bad,lr
  31         set_icc         0x2 0
  32         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  33
  34         set_spr_addr    bad,lr
  35         set_icc         0x3 0
  36         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  37
  38         set_psr_et      1
  39         set_spr_addr    ok4,lr
  40         set_icc         0x4 0
  41         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  42         fail
  43 ok4:
  44         set_psr_et      1
  45         set_spr_addr    ok5,lr
  46         set_icc         0x5 0
  47         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  48         fail
  49 ok5:
  50         set_spr_addr    bad,lr
  51         set_icc         0x6 0
  52         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  53
  54         set_spr_addr    bad,lr
  55         set_icc         0x7 0
  56         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  57
  58         set_psr_et      1
  59         set_spr_addr    ok8,lr
  60         set_icc         0x8 0
  61         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  62         fail
  63 ok8:
  64         set_psr_et      1
  65         set_spr_addr    ok9,lr
  66         set_icc         0x9 0
  67         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  68         fail
  69 ok9:
  70         set_spr_addr    bad,lr
  71         set_icc         0xa 0
  72         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  73
  74         set_spr_addr    bad,lr
  75         set_icc         0xb 0
  76         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  77
  78         set_psr_et      1
  79         set_spr_addr    okc,lr
  80         set_icc         0xc 0
  81         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  82         fail
  83 okc:
  84         set_psr_et      1
  85         set_spr_addr    okd,lr
  86         set_icc         0xd 0
  87         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  88         fail
  89 okd:
  90         set_spr_addr    bad,lr
  91         set_icc         0xe 0
  92         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  93
  94         set_spr_addr    bad,lr
  95         set_icc         0xf 0
  96         tinv            icc0,gr7,4      ; should branch to tbr + (128 + 4)*16
  97
  98         pass
  99 bad:
 100         fail