sim/testsuite/sim/frv/std.pcgs

   1 # frv parallel testcase for std $GRk,@($GRi,$GRj)
   2 # mach: all
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global add
   9 add:
  10         set_mem_limmed  0xbeef,0xdead,sp
  11         inc_gr_immed    -4,sp
  12         set_mem_limmed  0xdead,0xbeef,sp
  13         set_gr_immed    0,gr7
  14         set_gr_limmed   0xbeef,0xdead,gr8
  15         set_gr_limmed   0xdead,0xbeef,gr9
  16         std             gr8,@(sp,gr7)           ; non parallel
  17         test_mem_limmed 0xbeef,0xdead,sp
  18         inc_gr_immed    4,sp
  19         test_mem_limmed 0xdead,0xbeef,sp
  20
  21         set_mem_limmed  0xbeef,0xdead,sp
  22         inc_gr_immed    -4,sp
  23         set_mem_limmed  0xdead,0xbeef,sp
  24         set_gr_immed    4,gr7
  25         set_gr_limmed   0xbeef,0xdead,gr8
  26         set_gr_limmed   0xdead,0xbeef,gr9
  27         std.p           gr8,@(sp,gr0)           ; parallel
  28         setlos          0,gr8
  29         ld              @(sp,gr0),gr10
  30         ld              @(sp,gr7),gr11
  31         test_mem_limmed 0xbeef,0xdead,sp        ; memory is set
  32         inc_gr_immed    4,sp
  33         test_mem_limmed 0xdead,0xbeef,sp
  34         test_gr_immed   0xbeefdead,gr10         ; regs were pre-loaded
  35         test_gr_immed   0xdeadbeef,gr11         ; not this one
  36
  37         pass