sim/testsuite/sim/frv/interrupts/illinsn.cgs

   1 # FRV testcase
   2 # mach: fr500 fr550 fr400
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         .global tra
   9 tra:
  10         and_spr_immed   0x3fffffff,hsr0         ; no caches enabled
  11
  12         and_spr_immed   -4081,tbr               ; clear tbr.tt
  13         set_gr_spr      tbr,gr7
  14         inc_gr_immed    0x070,gr7               ; address of exception handler
  15         set_bctrlr_0_0  gr7
  16         inc_gr_immed    0x790,gr7               ; address of exception handler
  17         set_bctrlr_0_0  gr7
  18         set_spr_immed   128,lcr
  19         set_psr_et      1
  20         set_spr_addr    ok0,lr
  21
  22         set_gr_addr     ill1,gr7
  23         set_mem_immed   0x81f80000,gr7  ; unknown opcode: 7E
  24 ill1:   tira            gr0,0           ; should be overridden
  25 ill2:   nop                             ; also illegal, but prev has priority
  26 bad0:   fail
  27
  28         ; check interrupt
  29 ok0:    test_spr_addr   ill1,pcsr
  30         test_spr_immed  1,esfr1         ; esr0 active
  31         test_spr_bits   0x3f,0,0xb,esr0
  32         movsg           psr,gr28
  33         srli            gr28,28,gr28
  34         subicc          gr28,0x3,gr0,icc3 ; is fr550?
  35         beq             icc3,0,no_epcr
  36         test_spr_addr   ill1,epcr0
  37 no_epcr:
  38         pass