sim/testsuite/sim/frv/fr550/cmmachu.cgs

   1 # frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmmachu
   9 cmmachu:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_spr_immed   0,msr0
  13         set_accg_immed  0,accg0
  14         set_acc_immed   0,acc0
  15         set_accg_immed  0,accg1
  16         set_acc_immed   0,acc1
  17         set_fr_iimmed   3,2,fr7         ; multiply small numbers
  18         set_fr_iimmed   2,3,fr8
  19         cmmachu         fr7,fr8,acc0,cc0,1
  20         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  21         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  22         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  23         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  24         test_accg_immed         0,accg0
  25         test_acc_immed  6,acc0
  26         test_accg_immed         0,accg1
  27         test_acc_immed  6,acc1
  28
  29         set_fr_iimmed   1,2,fr7         ; multiply by 1
  30         set_fr_iimmed   2,1,fr8
  31         cmmachu         fr7,fr8,acc0,cc0,1
  32         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  33         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  34         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  35         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  36         test_accg_immed         0,accg0
  37         test_acc_immed  8,acc0
  38         test_accg_immed         0,accg1
  39         test_acc_immed  8,acc1
  40
  41         set_fr_iimmed   0,2,fr7         ; multiply by 0
  42         set_fr_iimmed   2,0,fr8
  43         cmmachu         fr7,fr8,acc0,cc0,1
  44         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  45         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  46         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  47         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  48         test_accg_immed         0,accg0
  49         test_acc_immed  8,acc0
  50         test_accg_immed         0,accg1
  51         test_acc_immed  8,acc1
  52
  53         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
  54         set_fr_iimmed   2,0x3fff,fr8
  55         cmmachu         fr7,fr8,acc0,cc0,1
  56         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  57         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  58         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  59         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  60         test_accg_immed         0,accg0
  61         test_acc_limmed 0x0000,0x8006,acc0
  62         test_accg_immed         0,accg1
  63         test_acc_limmed 0x0000,0x8006,acc1
  64
  65         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
  66         set_fr_iimmed   2,0x4000,fr8
  67         cmmachu         fr7,fr8,acc0,cc0,1
  68         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  69         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  70         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  71         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  72         test_accg_immed         0,accg0
  73         test_acc_limmed 0x0001,0x0006,acc0
  74         test_accg_immed         0,accg1
  75         test_acc_limmed 0x0001,0x0006,acc1
  76
  77         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
  78         set_fr_iimmed   2,0x8000,fr8
  79         cmmachu         fr7,fr8,acc0,cc4,1
  80         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  81         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  82         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  83         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  84         test_accg_immed         0,accg0
  85         test_acc_immed  0x00020006,acc0
  86         test_accg_immed         0,accg1
  87         test_acc_immed  0x00020006,acc1
  88
  89         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
  90         set_fr_iimmed   0x7fff,0x7fff,fr8
  91         cmmachu         fr7,fr8,acc0,cc4,1
  92         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  93         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  94         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  95         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  96         test_accg_immed         0,accg0
  97         test_acc_immed  0x40010007,acc0
  98         test_accg_immed         0,accg1
  99         test_acc_immed  0x40010007,acc1
 100
 101         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 102         set_fr_iimmed   0x8000,0x8000,fr8
 103         cmmachu         fr7,fr8,acc0,cc4,1
 104         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 105         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 106         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 107         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 108         test_accg_immed         0,accg0
 109         test_acc_limmed 0x8001,0x0007,acc0
 110         test_accg_immed         0,accg1
 111         test_acc_limmed 0x8001,0x0007,acc1
 112
 113         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 114         set_fr_iimmed   0xffff,0xffff,fr8
 115         cmmachu         fr7,fr8,acc0,cc4,1
 116         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 117         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 118         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 119         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 120         test_accg_immed         1,accg0
 121         test_acc_limmed 0x7fff,0x0008,acc0
 122         test_accg_immed         1,accg1
 123         test_acc_limmed 0x7fff,0x0008,acc1
 124
 125         set_accg_immed  0xff,accg0              ; saturation
 126         set_acc_immed   0xffffffff,acc0
 127         set_accg_immed  0xff,accg1
 128         set_acc_immed   0xffffffff,acc1
 129         set_fr_iimmed   1,1,fr7
 130         set_fr_iimmed   1,1,fr8
 131         cmmachu         fr7,fr8,acc0,cc4,1
 132         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
 133         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 134         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 135         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 136         test_accg_immed         0xff,accg0
 137         test_acc_limmed 0xffff,0xffff,acc0
 138         test_accg_immed         0xff,accg1
 139         test_acc_limmed 0xffff,0xffff,acc1
 140
 141         set_fr_iimmed   0xffff,0x0000,fr7
 142         set_fr_iimmed   0xffff,0xffff,fr8
 143         cmmachu         fr7,fr8,acc0,cc4,1
 144         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 145         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 146         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 147         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 148         test_accg_immed         0xff,accg0
 149         test_acc_limmed 0xffff,0xffff,acc0
 150         test_accg_immed         0xff,accg1
 151         test_acc_limmed 0xffff,0xffff,acc1
 152
 153         set_spr_immed   0,msr0
 154         set_accg_immed  0,accg0
 155         set_acc_immed   0,acc0
 156         set_accg_immed  0,accg1
 157         set_acc_immed   0,acc1
 158         set_fr_iimmed   3,2,fr7         ; multiply small numbers
 159         set_fr_iimmed   2,3,fr8
 160         cmmachu         fr7,fr8,acc0,cc1,0
 161         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 162         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 163         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 164         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 165         test_accg_immed         0,accg0
 166         test_acc_immed  6,acc0
 167         test_accg_immed         0,accg1
 168         test_acc_immed  6,acc1
 169
 170         set_fr_iimmed   1,2,fr7         ; multiply by 1
 171         set_fr_iimmed   2,1,fr8
 172         cmmachu         fr7,fr8,acc0,cc1,0
 173         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 174         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 175         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 176         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 177         test_accg_immed         0,accg0
 178         test_acc_immed  8,acc0
 179         test_accg_immed         0,accg1
 180         test_acc_immed  8,acc1
 181
 182         set_fr_iimmed   0,2,fr7         ; multiply by 0
 183         set_fr_iimmed   2,0,fr8
 184         cmmachu         fr7,fr8,acc0,cc1,0
 185         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 186         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 187         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 188         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 189         test_accg_immed         0,accg0
 190         test_acc_immed  8,acc0
 191         test_accg_immed         0,accg1
 192         test_acc_immed  8,acc1
 193
 194         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
 195         set_fr_iimmed   2,0x3fff,fr8
 196         cmmachu         fr7,fr8,acc0,cc1,0
 197         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 198         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 199         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 200         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 201         test_accg_immed         0,accg0
 202         test_acc_limmed 0x0000,0x8006,acc0
 203         test_accg_immed         0,accg1
 204         test_acc_limmed 0x0000,0x8006,acc1
 205
 206         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
 207         set_fr_iimmed   2,0x4000,fr8
 208         cmmachu         fr7,fr8,acc0,cc1,0
 209         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 210         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 211         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 212         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 213         test_accg_immed         0,accg0
 214         test_acc_limmed 0x0001,0x0006,acc0
 215         test_accg_immed         0,accg1
 216         test_acc_limmed 0x0001,0x0006,acc1
 217
 218         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
 219         set_fr_iimmed   2,0x8000,fr8
 220         cmmachu         fr7,fr8,acc0,cc5,0
 221         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 222         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 223         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 224         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 225         test_accg_immed         0,accg0
 226         test_acc_immed  0x00020006,acc0
 227         test_accg_immed         0,accg1
 228         test_acc_immed  0x00020006,acc1
 229
 230         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
 231         set_fr_iimmed   0x7fff,0x7fff,fr8
 232         cmmachu         fr7,fr8,acc0,cc5,0
 233         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 234         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 235         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 236         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 237         test_accg_immed         0,accg0
 238         test_acc_immed  0x40010007,acc0
 239         test_accg_immed         0,accg1
 240         test_acc_immed  0x40010007,acc1
 241
 242         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 243         set_fr_iimmed   0x8000,0x8000,fr8
 244         cmmachu         fr7,fr8,acc0,cc5,0
 245         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 246         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 247         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 248         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 249         test_accg_immed         0,accg0
 250         test_acc_limmed 0x8001,0x0007,acc0
 251         test_accg_immed         0,accg1
 252         test_acc_limmed 0x8001,0x0007,acc1
 253
 254         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 255         set_fr_iimmed   0xffff,0xffff,fr8
 256         cmmachu         fr7,fr8,acc0,cc5,0
 257         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 258         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 259         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 260         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 261         test_accg_immed         1,accg0
 262         test_acc_limmed 0x7fff,0x0008,acc0
 263         test_accg_immed         1,accg1
 264         test_acc_limmed 0x7fff,0x0008,acc1
 265
 266         set_accg_immed  0xff,accg0              ; saturation
 267         set_acc_immed   0xffffffff,acc0
 268         set_accg_immed  0xff,accg1
 269         set_acc_immed   0xffffffff,acc1
 270         set_fr_iimmed   1,1,fr7
 271         set_fr_iimmed   1,1,fr8
 272         cmmachu         fr7,fr8,acc0,cc5,0
 273         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
 274         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 275         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 276         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 277         test_accg_immed         0xff,accg0
 278         test_acc_limmed 0xffff,0xffff,acc0
 279         test_accg_immed         0xff,accg1
 280         test_acc_limmed 0xffff,0xffff,acc1
 281
 282         set_fr_iimmed   0xffff,0x0000,fr7
 283         set_fr_iimmed   0xffff,0xffff,fr8
 284         cmmachu         fr7,fr8,acc0,cc5,0
 285         test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
 286         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 287         test_spr_bits   1,0,1,msr0              ; msr0.aovf is set
 288         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt is set
 289         test_accg_immed         0xff,accg0
 290         test_acc_limmed 0xffff,0xffff,acc0
 291         test_accg_immed         0xff,accg1
 292         test_acc_limmed 0xffff,0xffff,acc1
 293
 294         set_spr_immed   0,msr0
 295         set_accg_immed  0x00000011,accg0
 296         set_acc_immed   0x11111111,acc0
 297         set_accg_immed  0x00000022,accg1
 298         set_acc_immed   0x22222222,acc1
 299         set_fr_iimmed   3,2,fr7         ; multiply small numbers
 300         set_fr_iimmed   2,3,fr8
 301         cmmachu         fr7,fr8,acc0,cc0,0
 302         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 303         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 304         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 305         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 306         test_accg_immed         0x00000011,accg0
 307         test_acc_immed  0x11111111,acc0
 308         test_accg_immed         0x00000022,accg1
 309         test_acc_immed  0x22222222,acc1
 310
 311         set_fr_iimmed   1,2,fr7         ; multiply by 1
 312         set_fr_iimmed   2,1,fr8
 313         cmmachu         fr7,fr8,acc0,cc0,0
 314         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 315         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 316         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 317         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 318         test_accg_immed         0x00000011,accg0
 319         test_acc_immed  0x11111111,acc0
 320         test_accg_immed         0x00000022,accg1
 321         test_acc_immed  0x22222222,acc1
 322
 323         set_fr_iimmed   0,2,fr7         ; multiply by 0
 324         set_fr_iimmed   2,0,fr8
 325         cmmachu         fr7,fr8,acc0,cc0,0
 326         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 327         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 328         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 329         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 330         test_accg_immed         0x00000011,accg0
 331         test_acc_immed  0x11111111,acc0
 332         test_accg_immed         0x00000022,accg1
 333         test_acc_immed  0x22222222,acc1
 334
 335         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
 336         set_fr_iimmed   2,0x3fff,fr8
 337         cmmachu         fr7,fr8,acc0,cc0,0
 338         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 339         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 340         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 341         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 342         test_accg_immed         0x00000011,accg0
 343         test_acc_immed  0x11111111,acc0
 344         test_accg_immed         0x00000022,accg1
 345         test_acc_immed  0x22222222,acc1
 346
 347         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
 348         set_fr_iimmed   2,0x4000,fr8
 349         cmmachu         fr7,fr8,acc0,cc0,0
 350         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 351         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 352         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 353         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 354         test_accg_immed         0x00000011,accg0
 355         test_acc_immed  0x11111111,acc0
 356         test_accg_immed         0x00000022,accg1
 357         test_acc_immed  0x22222222,acc1
 358
 359         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
 360         set_fr_iimmed   2,0x8000,fr8
 361         cmmachu         fr7,fr8,acc0,cc4,0
 362         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 363         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 364         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 365         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 366         test_accg_immed         0x00000011,accg0
 367         test_acc_immed  0x11111111,acc0
 368         test_accg_immed         0x00000022,accg1
 369         test_acc_immed  0x22222222,acc1
 370
 371         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
 372         set_fr_iimmed   0x7fff,0x7fff,fr8
 373         cmmachu         fr7,fr8,acc0,cc4,0
 374         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 375         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 376         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 377         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 378         test_accg_immed         0x00000011,accg0
 379         test_acc_immed  0x11111111,acc0
 380         test_accg_immed         0x00000022,accg1
 381         test_acc_immed  0x22222222,acc1
 382
 383         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 384         set_fr_iimmed   0x8000,0x8000,fr8
 385         cmmachu         fr7,fr8,acc0,cc4,0
 386         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 387         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 388         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 389         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 390         test_accg_immed         0x00000011,accg0
 391         test_acc_immed  0x11111111,acc0
 392         test_accg_immed         0x00000022,accg1
 393         test_acc_immed  0x22222222,acc1
 394
 395         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 396         set_fr_iimmed   0xffff,0xffff,fr8
 397         cmmachu         fr7,fr8,acc0,cc4,0
 398         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 399         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 400         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 401         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 402         test_accg_immed         0x00000011,accg0
 403         test_acc_immed  0x11111111,acc0
 404         test_accg_immed         0x00000022,accg1
 405         test_acc_immed  0x22222222,acc1
 406
 407         set_accg_immed  0xff,accg0              ; saturation
 408         set_acc_immed   0xffffffff,acc0
 409         set_accg_immed  0xff,accg1
 410         set_acc_immed   0xffffffff,acc1
 411         set_fr_iimmed   1,1,fr7
 412         set_fr_iimmed   1,1,fr8
 413         cmmachu         fr7,fr8,acc0,cc4,0
 414         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 415         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 416         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 417         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 418         test_accg_immed         0xff,accg0              ; saturation
 419         test_acc_immed  0xffffffff,acc0
 420         test_accg_immed         0xff,accg1
 421         test_acc_immed  0xffffffff,acc1
 422
 423         set_fr_iimmed   0xffff,0x0000,fr7
 424         set_fr_iimmed   0xffff,0xffff,fr8
 425         cmmachu         fr7,fr8,acc0,cc4,0
 426         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 427         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 428         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 429         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 430         test_accg_immed         0xff,accg0              ; saturation
 431         test_acc_immed  0xffffffff,acc0
 432         test_accg_immed         0xff,accg1
 433         test_acc_immed  0xffffffff,acc1
 434
 435         set_spr_immed   0,msr0
 436         set_accg_immed  0x00000011,accg0
 437         set_acc_immed   0x11111111,acc0
 438         set_accg_immed  0x00000022,accg1
 439         set_acc_immed   0x22222222,acc1
 440         set_fr_iimmed   3,2,fr7         ; multiply small numbers
 441         set_fr_iimmed   2,3,fr8
 442         cmmachu         fr7,fr8,acc0,cc1,1
 443         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 444         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 445         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 446         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 447         test_accg_immed         0x00000011,accg0
 448         test_acc_immed  0x11111111,acc0
 449         test_accg_immed         0x00000022,accg1
 450         test_acc_immed  0x22222222,acc1
 451
 452         set_fr_iimmed   1,2,fr7         ; multiply by 1
 453         set_fr_iimmed   2,1,fr8
 454         cmmachu         fr7,fr8,acc0,cc1,1
 455         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 456         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 457         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 458         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 459         test_accg_immed         0x00000011,accg0
 460         test_acc_immed  0x11111111,acc0
 461         test_accg_immed         0x00000022,accg1
 462         test_acc_immed  0x22222222,acc1
 463
 464         set_fr_iimmed   0,2,fr7         ; multiply by 0
 465         set_fr_iimmed   2,0,fr8
 466         cmmachu         fr7,fr8,acc0,cc1,1
 467         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 468         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 469         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 470         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 471         test_accg_immed         0x00000011,accg0
 472         test_acc_immed  0x11111111,acc0
 473         test_accg_immed         0x00000022,accg1
 474         test_acc_immed  0x22222222,acc1
 475
 476         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
 477         set_fr_iimmed   2,0x3fff,fr8
 478         cmmachu         fr7,fr8,acc0,cc1,1
 479         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 480         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 481         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 482         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 483         test_accg_immed         0x00000011,accg0
 484         test_acc_immed  0x11111111,acc0
 485         test_accg_immed         0x00000022,accg1
 486         test_acc_immed  0x22222222,acc1
 487
 488         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
 489         set_fr_iimmed   2,0x4000,fr8
 490         cmmachu         fr7,fr8,acc0,cc1,1
 491         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 492         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 493         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 494         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 495         test_accg_immed         0x00000011,accg0
 496         test_acc_immed  0x11111111,acc0
 497         test_accg_immed         0x00000022,accg1
 498         test_acc_immed  0x22222222,acc1
 499
 500         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
 501         set_fr_iimmed   2,0x8000,fr8
 502         cmmachu         fr7,fr8,acc0,cc5,1
 503         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 504         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 505         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 506         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 507         test_accg_immed         0x00000011,accg0
 508         test_acc_immed  0x11111111,acc0
 509         test_accg_immed         0x00000022,accg1
 510         test_acc_immed  0x22222222,acc1
 511
 512         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
 513         set_fr_iimmed   0x7fff,0x7fff,fr8
 514         cmmachu         fr7,fr8,acc0,cc5,1
 515         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 516         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 517         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 518         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 519         test_accg_immed         0x00000011,accg0
 520         test_acc_immed  0x11111111,acc0
 521         test_accg_immed         0x00000022,accg1
 522         test_acc_immed  0x22222222,acc1
 523
 524         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 525         set_fr_iimmed   0x8000,0x8000,fr8
 526         cmmachu         fr7,fr8,acc0,cc5,1
 527         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 528         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 529         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 530         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 531         test_accg_immed         0x00000011,accg0
 532         test_acc_immed  0x11111111,acc0
 533         test_accg_immed         0x00000022,accg1
 534         test_acc_immed  0x22222222,acc1
 535
 536         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 537         set_fr_iimmed   0xffff,0xffff,fr8
 538         cmmachu         fr7,fr8,acc0,cc5,1
 539         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 540         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 541         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 542         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 543         test_accg_immed         0x00000011,accg0
 544         test_acc_immed  0x11111111,acc0
 545         test_accg_immed         0x00000022,accg1
 546         test_acc_immed  0x22222222,acc1
 547
 548         set_accg_immed  0xff,accg0              ; saturation
 549         set_acc_immed   0xffffffff,acc0
 550         set_accg_immed  0xff,accg1
 551         set_acc_immed   0xffffffff,acc1
 552         set_fr_iimmed   1,1,fr7
 553         set_fr_iimmed   1,1,fr8
 554         cmmachu         fr7,fr8,acc0,cc5,1
 555         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 556         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 557         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 558         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 559         test_accg_immed         0xff,accg0              ; saturation
 560         test_acc_immed  0xffffffff,acc0
 561         test_accg_immed         0xff,accg1
 562         test_acc_immed  0xffffffff,acc1
 563
 564         set_fr_iimmed   0xffff,0x0000,fr7
 565         set_fr_iimmed   0xffff,0xffff,fr8
 566         cmmachu         fr7,fr8,acc0,cc5,1
 567         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 568         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 569         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 570         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 571         test_accg_immed         0xff,accg0              ; saturation
 572         test_acc_immed  0xffffffff,acc0
 573         test_accg_immed         0xff,accg1
 574         test_acc_immed  0xffffffff,acc1
 575
 576         set_spr_immed   0,msr0
 577         set_accg_immed  0x00000011,accg0
 578         set_acc_immed   0x11111111,acc0
 579         set_accg_immed  0x00000022,accg1
 580         set_acc_immed   0x22222222,acc1
 581         set_fr_iimmed   3,2,fr7         ; multiply small numbers
 582         set_fr_iimmed   2,3,fr8
 583         cmmachu         fr7,fr8,acc0,cc2,1
 584         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 585         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 586         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 587         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 588         test_accg_immed         0x00000011,accg0
 589         test_acc_immed  0x11111111,acc0
 590         test_accg_immed         0x00000022,accg1
 591         test_acc_immed  0x22222222,acc1
 592
 593         set_fr_iimmed   1,2,fr7         ; multiply by 1
 594         set_fr_iimmed   2,1,fr8
 595         cmmachu         fr7,fr8,acc0,cc2,1
 596         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 597         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 598         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 599         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 600         test_accg_immed         0x00000011,accg0
 601         test_acc_immed  0x11111111,acc0
 602         test_accg_immed         0x00000022,accg1
 603         test_acc_immed  0x22222222,acc1
 604
 605         set_fr_iimmed   0,2,fr7         ; multiply by 0
 606         set_fr_iimmed   2,0,fr8
 607         cmmachu         fr7,fr8,acc0,cc2,1
 608         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 609         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 610         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 611         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 612         test_accg_immed         0x00000011,accg0
 613         test_acc_immed  0x11111111,acc0
 614         test_accg_immed         0x00000022,accg1
 615         test_acc_immed  0x22222222,acc1
 616
 617         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
 618         set_fr_iimmed   2,0x3fff,fr8
 619         cmmachu         fr7,fr8,acc0,cc2,1
 620         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 621         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 622         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 623         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 624         test_accg_immed         0x00000011,accg0
 625         test_acc_immed  0x11111111,acc0
 626         test_accg_immed         0x00000022,accg1
 627         test_acc_immed  0x22222222,acc1
 628
 629         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
 630         set_fr_iimmed   2,0x4000,fr8
 631         cmmachu         fr7,fr8,acc0,cc2,1
 632         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 633         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 634         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 635         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 636         test_accg_immed         0x00000011,accg0
 637         test_acc_immed  0x11111111,acc0
 638         test_accg_immed         0x00000022,accg1
 639         test_acc_immed  0x22222222,acc1
 640
 641         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
 642         set_fr_iimmed   2,0x8000,fr8
 643         cmmachu         fr7,fr8,acc0,cc6,1
 644         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 645         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 646         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 647         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 648         test_accg_immed         0x00000011,accg0
 649         test_acc_immed  0x11111111,acc0
 650         test_accg_immed         0x00000022,accg1
 651         test_acc_immed  0x22222222,acc1
 652
 653         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
 654         set_fr_iimmed   0x7fff,0x7fff,fr8
 655         cmmachu         fr7,fr8,acc0,cc6,1
 656         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 657         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 658         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 659         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 660         test_accg_immed         0x00000011,accg0
 661         test_acc_immed  0x11111111,acc0
 662         test_accg_immed         0x00000022,accg1
 663         test_acc_immed  0x22222222,acc1
 664
 665         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 666         set_fr_iimmed   0x8000,0x8000,fr8
 667         cmmachu         fr7,fr8,acc0,cc6,1
 668         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 669         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 670         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 671         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 672         test_accg_immed         0x00000011,accg0
 673         test_acc_immed  0x11111111,acc0
 674         test_accg_immed         0x00000022,accg1
 675         test_acc_immed  0x22222222,acc1
 676
 677         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 678         set_fr_iimmed   0xffff,0xffff,fr8
 679         cmmachu         fr7,fr8,acc0,cc6,1
 680         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 681         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 682         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 683         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 684         test_accg_immed         0x00000011,accg0
 685         test_acc_immed  0x11111111,acc0
 686         test_accg_immed         0x00000022,accg1
 687         test_acc_immed  0x22222222,acc1
 688
 689         set_accg_immed  0xff,accg0              ; saturation
 690         set_acc_immed   0xffffffff,acc0
 691         set_accg_immed  0xff,accg1
 692         set_acc_immed   0xffffffff,acc1
 693         set_fr_iimmed   1,1,fr7
 694         set_fr_iimmed   1,1,fr8
 695         cmmachu         fr7,fr8,acc0,cc6,1
 696         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 697         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 698         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 699         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 700         test_accg_immed         0xff,accg0              ; saturation
 701         test_acc_immed  0xffffffff,acc0
 702         test_accg_immed         0xff,accg1
 703         test_acc_immed  0xffffffff,acc1
 704
 705         set_fr_iimmed   0xffff,0x0000,fr7
 706         set_fr_iimmed   0xffff,0xffff,fr8
 707         cmmachu         fr7,fr8,acc0,cc6,1
 708         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 709         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 710         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 711         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 712         test_accg_immed         0xff,accg0              ; saturation
 713         test_acc_immed  0xffffffff,acc0
 714         test_accg_immed         0xff,accg1
 715         test_acc_immed  0xffffffff,acc1
 716 ;
 717         set_spr_immed   0,msr0
 718         set_accg_immed  0x00000011,accg0
 719         set_acc_immed   0x11111111,acc0
 720         set_accg_immed  0x00000022,accg1
 721         set_acc_immed   0x22222222,acc1
 722         set_fr_iimmed   3,2,fr7         ; multiply small numbers
 723         set_fr_iimmed   2,3,fr8
 724         cmmachu         fr7,fr8,acc0,cc3,1
 725         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 726         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 727         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 728         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 729         test_accg_immed         0x00000011,accg0
 730         test_acc_immed  0x11111111,acc0
 731         test_accg_immed         0x00000022,accg1
 732         test_acc_immed  0x22222222,acc1
 733
 734         set_fr_iimmed   1,2,fr7         ; multiply by 1
 735         set_fr_iimmed   2,1,fr8
 736         cmmachu         fr7,fr8,acc0,cc3,1
 737         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 738         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 739         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 740         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 741         test_accg_immed         0x00000011,accg0
 742         test_acc_immed  0x11111111,acc0
 743         test_accg_immed         0x00000022,accg1
 744         test_acc_immed  0x22222222,acc1
 745
 746         set_fr_iimmed   0,2,fr7         ; multiply by 0
 747         set_fr_iimmed   2,0,fr8
 748         cmmachu         fr7,fr8,acc0,cc3,1
 749         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 750         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 751         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 752         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 753         test_accg_immed         0x00000011,accg0
 754         test_acc_immed  0x11111111,acc0
 755         test_accg_immed         0x00000022,accg1
 756         test_acc_immed  0x22222222,acc1
 757
 758         set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
 759         set_fr_iimmed   2,0x3fff,fr8
 760         cmmachu         fr7,fr8,acc0,cc3,1
 761         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 762         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 763         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 764         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 765         test_accg_immed         0x00000011,accg0
 766         test_acc_immed  0x11111111,acc0
 767         test_accg_immed         0x00000022,accg1
 768         test_acc_immed  0x22222222,acc1
 769
 770         set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
 771         set_fr_iimmed   2,0x4000,fr8
 772         cmmachu         fr7,fr8,acc0,cc3,1
 773         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 774         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 775         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 776         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 777         test_accg_immed         0x00000011,accg0
 778         test_acc_immed  0x11111111,acc0
 779         test_accg_immed         0x00000022,accg1
 780         test_acc_immed  0x22222222,acc1
 781
 782         set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
 783         set_fr_iimmed   2,0x8000,fr8
 784         cmmachu         fr7,fr8,acc0,cc7,1
 785         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 786         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 787         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 788         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 789         test_accg_immed         0x00000011,accg0
 790         test_acc_immed  0x11111111,acc0
 791         test_accg_immed         0x00000022,accg1
 792         test_acc_immed  0x22222222,acc1
 793
 794         set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
 795         set_fr_iimmed   0x7fff,0x7fff,fr8
 796         cmmachu         fr7,fr8,acc0,cc7,1
 797         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 798         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 799         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 800         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 801         test_accg_immed         0x00000011,accg0
 802         test_acc_immed  0x11111111,acc0
 803         test_accg_immed         0x00000022,accg1
 804         test_acc_immed  0x22222222,acc1
 805
 806         set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
 807         set_fr_iimmed   0x8000,0x8000,fr8
 808         cmmachu         fr7,fr8,acc0,cc7,1
 809         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 810         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 811         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 812         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 813         test_accg_immed         0x00000011,accg0
 814         test_acc_immed  0x11111111,acc0
 815         test_accg_immed         0x00000022,accg1
 816         test_acc_immed  0x22222222,acc1
 817
 818         set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
 819         set_fr_iimmed   0xffff,0xffff,fr8
 820         cmmachu         fr7,fr8,acc0,cc7,1
 821         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 822         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 823         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 824         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 825         test_accg_immed         0x00000011,accg0
 826         test_acc_immed  0x11111111,acc0
 827         test_accg_immed         0x00000022,accg1
 828         test_acc_immed  0x22222222,acc1
 829
 830         set_accg_immed  0xff,accg0              ; saturation
 831         set_acc_immed   0xffffffff,acc0
 832         set_accg_immed  0xff,accg1
 833         set_acc_immed   0xffffffff,acc1
 834         set_fr_iimmed   1,1,fr7
 835         set_fr_iimmed   1,1,fr8
 836         cmmachu         fr7,fr8,acc0,cc7,1
 837         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 838         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 839         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 840         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 841         test_accg_immed         0xff,accg0              ; saturation
 842         test_acc_immed  0xffffffff,acc0
 843         test_accg_immed         0xff,accg1
 844         test_acc_immed  0xffffffff,acc1
 845
 846         set_fr_iimmed   0xffff,0x0000,fr7
 847         set_fr_iimmed   0xffff,0xffff,fr8
 848         cmmachu         fr7,fr8,acc0,cc7,1
 849         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 850         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 851         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 852         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 853         test_accg_immed         0xff,accg0              ; saturation
 854         test_acc_immed  0xffffffff,acc0
 855         test_accg_immed         0xff,accg1
 856         test_acc_immed  0xffffffff,acc1
 857
 858         pass