sim/testsuite/sim/fr30/div0u.cgs

   1 # fr30 testcase for div0u $Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global div0u
  10 div0u:
  11         ; Test div0u $Rj,$Ri
  12         ; operand register has no effect
  13         mvi_h_gr        0xdeadbeef,r2
  14         mvi_h_dr        0xdeadbeef,mdh
  15         mvi_h_dr        0x0ffffff0,mdl
  16         set_dbits       0x3             ; Set opposite of expected
  17         set_cc          0x0f            ; Condition codes should not change
  18         div0u           r2
  19         test_cc         1 1 1 1
  20         test_h_gr       0xdeadbeef,r2
  21         test_h_dr       0x00000000,mdh
  22         test_h_dr       0x0ffffff0,mdl
  23         test_dbits      0x0
  24
  25         pass