sim/testsuite/sim/bfin/vec-neg.S

   1 # Blackfin testcase for vector negate instruction
   2 # mach: bfin
   3
   4 #include "test.h"
   5
   6         .include "testutils.inc"
   7
   8         start
   9
  10         .global _test
  11 _test:
  12         R6 = ASTAT;
  13         R0.H = 0x1234;
  14         R0.L = 0xcdef;
  15         R1 = -R0 (V);
  16         R7 = ASTAT;
  17         R2.H = 0xedcc;
  18         R2.L = 0x3211;
  19         CC = R1 == R2;
  20         IF !CC JUMP 1f;
  21         /* CLEARED: AZ V V_COPY AC0 AC0_COPY AC1 */
  22         R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
  23         R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
  24         R4 = R7 & R3;
  25         CC = R4 == 0;
  26         IF !CC JUMP 1f;
  27         /* SET: AN */
  28         R3.H = HI(_AN);
  29         R3.L = LO(_AN);
  30         R4 = R7 & R3;
  31         CC = R3 == R4;
  32         IF !CC JUMP 1f;
  33         /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS */
  34         R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS);
  35         R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS);
  36         R4 = R6 & R3;
  37         R5 = R7 & R3;
  38         CC = R4 == R5;
  39         IF !CC JUMP 1f;
  40         pass
  41 1:
  42         fail