sim/testsuite/sim/bfin/lp0.s

   1 // Assert that loops can have coincidental loop ends.
   2 # mach: bfin
   3
   4 .include "testutils.inc"
   5         start
   6
   7
   8         P0 = 3;
   9         R1 = 0;
  10         LSETUP ( out0 , out1 ) LC0 = P0;
  11 out0:
  12         LSETUP ( out1 , out1 ) LC1 = P0;
  13 out1:
  14         R1 += 1;
  15
  16         DBGA ( R1.L , 9 );
  17         pass