sim/testsuite/sim/bfin/hwloop-lt-bits.s

   1 # Blackfin testcase for HW Loops (LT) LSB behavior
   2 # mach: bfin
   3
   4         .include "testutils.inc"
   5
   6         start
   7
   8         # Loading LT should always clear LSB
   9         imm32 R6, 0xaaaa5555
  10         R4 = R6;
  11         BITCLR (R4, 0);
  12
  13         LT0 = R6;
  14         LT1 = R6;
  15
  16         R0 = LT0;
  17         CC = R0 == R4;
  18         IF ! CC JUMP 1f;
  19
  20         R0 = LT1;
  21         CC = R0 == R4;
  22         IF ! CC JUMP 1f;
  23
  24         pass
  25 1:      fail