1 # Blackfin testcase for having RETI LSB set correctly when self nested
3 # sim: --environment operating
6 .include "testutils.inc"
14 loadsym R1, _fail_lvl;
15 [P5 + 4] = R1; /* IVG12 */
16 [P5 + 12] = R1; /* IVG14 */
26 # Enable IVG11/IVG13/IVG14 but not IVG12
34 # Counter to keep track of nesting depth
37 # Lower ourselves to IVG11
38 loadsym R4, _fail_lvl;
46 # This IVG makes sure RETI LSB is set correctly on transition in (RAISE)
50 # Make sure we are indeed at IVG11
54 IF !CC JUMP _fail_lvl;
56 # Make sure LSB of RETI is set only on first pass
57 CC = ! BITTST (R0, 0);
62 IF !CC JUMP _fail_lvl;
64 # Nest ourselves a few times
74 # Move down to IVG13 for next test
75 1: loadsym R4, _fail_lvl;
79 # This IVG makes sure RETI LSB is respected on transition out (RTI)
83 # Make sure we are indeed at IVG13
87 IF !CC JUMP _fail_lvl;
89 # RETI LSB should be set when re-entering IVG13
90 CC = ! BITTST (R0, 0);
95 IF !CC JUMP _fail_lvl;
97 # Should get here only after a few IVG11 tests
101 # Make sure IVG13 isn't pending
104 CC = BITTST (R1, 13);
105 IF CC JUMP _fail_lvl;
107 # Manually set RETI to with LSB set so we return there