sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s

   1 //Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp
   2 // Spec Reference: regmv dr-dep no stall
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         imm32 r0, 0x00000001;
   9         imm32 r1, 0x00110001;
  10         imm32 r2, 0x00220002;
  11         imm32 r3, 0x00330003;
  12         imm32 r4, 0x00440004;
  13         imm32 r5, 0x00550005;
  14         imm32 r6, 0x00660006;
  15         imm32 r7, 0x00770007;
  16 // R-reg to R-reg: no stall
  17         R0 = R0;
  18         R1 = R0;
  19         R2 = R1;
  20         R3 = R2;
  21         R4 = R3;
  22         R5 = R4;
  23         R6 = R5;
  24         R7 = R6;
  25         R0 = R7;
  26
  27         CHECKREG r0, 0x00000001;
  28         CHECKREG r1, 0x00000001;
  29         CHECKREG r2, 0x00000001;
  30         CHECKREG r3, 0x00000001;
  31         CHECKREG r4, 0x00000001;
  32         CHECKREG r5, 0x00000001;
  33         CHECKREG r6, 0x00000001;
  34         CHECKREG r7, 0x00000001;
  35
  36 //imm32 p0, 0x00001111;
  37         imm32 p1, 0x22223333;
  38         imm32 p2, 0x44445555;
  39         imm32 p3, 0x66667777;
  40         imm32 p4, 0x88889999;
  41         imm32 p5, 0xaaaabbbb;
  42         imm32 fp, 0xccccdddd;
  43         imm32 sp, 0xeeeeffff;
  44
  45 // P-reg to R-reg to I,M reg: no stall
  46         R0 = P0;
  47         I0 = R0;
  48         R1 = P1;
  49         I1 = R1;
  50         R2 = P2;
  51         I2 = R2;
  52         R3 = P3;
  53         I3 = R3;
  54         R4 = P4;
  55         M0 = R4;
  56         R5 = P5;
  57         M1 = R5;
  58         R6 = FP;
  59         M2 = R6;
  60         R7 = SP;
  61         M3 = R7;
  62
  63         CHECKREG r1, 0x22223333;
  64         CHECKREG r2, 0x44445555;
  65         CHECKREG r3, 0x66667777;
  66         CHECKREG r4, 0x88889999;
  67         CHECKREG r5, 0xAAAABBBB;
  68         CHECKREG r6, 0xCCCCDDDD;
  69         CHECKREG r7, 0xEEEEFFFF;
  70
  71         R0 = M3;
  72         R1 = M2;
  73         R2 = M1;
  74         R3 = M0;
  75         R4 = I3;
  76         R5 = I2;
  77         R6 = I1;
  78         R7 = I0;
  79         CHECKREG r0, 0xEEEEFFFF;
  80         CHECKREG r1, 0xCCCCDDDD;
  81         CHECKREG r2, 0xAAAABBBB;
  82         CHECKREG r3, 0x88889999;
  83         CHECKREG r4, 0x66667777;
  84         CHECKREG r5, 0x44445555;
  85         CHECKREG r6, 0x22223333;
  86
  87         imm32 i0, 0x00001111;
  88         imm32 i1, 0x22223333;
  89         imm32 i2, 0x44445555;
  90         imm32 i3, 0x66667777;
  91         imm32 m0, 0x88889999;
  92         imm32 m0, 0xaaaabbbb;
  93         imm32 m0, 0xccccdddd;
  94         imm32 m0, 0xeeeeffff;
  95
  96 // I,M-reg to R-reg to P-reg: no stall
  97         R0 = I0;
  98         P1 = R0;
  99         R1 = I1;
 100         P1 = R1;
 101         R2 = I2;
 102         P2 = R2;
 103         R3 = I3;
 104         P3 = R3;
 105         R4 = M0;
 106         P4 = R4;
 107         R5 = M1;
 108         P5 = R5;
 109         R6 = M2;
 110         SP = R6;
 111         R7 = M3;
 112         FP = R7;
 113
 114         CHECKREG p1, 0x22223333;
 115         CHECKREG p2, 0x44445555;
 116         CHECKREG p3, 0x66667777;
 117         CHECKREG p4, 0xEEEEFFFF;
 118         CHECKREG p5, 0xAAAABBBB;
 119         CHECKREG sp, 0xCCCCDDDD;
 120         CHECKREG fp, 0xEEEEFFFF;
 121
 122         imm32 i0, 0x10001111;
 123         imm32 i1, 0x12221333;
 124         imm32 i2, 0x14441555;
 125         imm32 i3, 0x16661777;
 126         imm32 m0, 0x18881999;
 127         imm32 m1, 0x1aaa1bbb;
 128         imm32 m2, 0x1ccc1ddd;
 129         imm32 m3, 0x1eee1fff;
 130
 131 // I,M-reg to R-reg to L,B reg: no stall
 132         R0 = I0;
 133         L0 = R0;
 134         R1 = I1;
 135         L1 = R1;
 136         R2 = I2;
 137         L2 = R2;
 138         R3 = I3;
 139         L3 = R3;
 140         R4 = M0;
 141         B0 = R4;
 142         R5 = M1;
 143         B1 = R5;
 144         R6 = M2;
 145         B2 = R6;
 146         R7 = M3;
 147         B3 = R7;
 148
 149         CHECKREG r0, 0x10001111;
 150         CHECKREG r1, 0x12221333;
 151         CHECKREG r2, 0x14441555;
 152         CHECKREG r3, 0x16661777;
 153         CHECKREG r4, 0x18881999;
 154         CHECKREG r5, 0x1AAA1BBB;
 155         CHECKREG r6, 0x1CCC1DDD;
 156         CHECKREG r7, 0x1EEE1FFF;
 157
 158         R0 = L3;
 159         R1 = L2;
 160         R2 = L1;
 161         R3 = L0;
 162         R4 = B3;
 163         R5 = B2;
 164         R6 = B1;
 165         R7 = B0;
 166         CHECKREG r0, 0x16661777;
 167         CHECKREG r1, 0x14441555;
 168         CHECKREG r2, 0x12221333;
 169         CHECKREG r3, 0x10001111;
 170         CHECKREG r4, 0x1EEE1FFF;
 171         CHECKREG r5, 0x1CCC1DDD;
 172         CHECKREG r6, 0x1AAA1BBB;
 173         CHECKREG r7, 0x18881999;
 174
 175         imm32 l0, 0x20003111;
 176         imm32 l1, 0x22223333;
 177         imm32 l2, 0x24443555;
 178         imm32 l3, 0x26663777;
 179         imm32 b0, 0x28883999;
 180         imm32 b0, 0x2aaa3bbb;
 181         imm32 b0, 0x2ccc3ddd;
 182         imm32 b0, 0x2eee3fff;
 183
 184 // L,B-reg to R-reg to I,M reg: no stall
 185         R0 = L0;
 186         I0 = R0;
 187         R1 = L1;
 188         I1 = R1;
 189         R2 = L2;
 190         I2 = R2;
 191         R3 = L3;
 192         I3 = R3;
 193         R4 = B0;
 194         M0 = R4;
 195         R5 = B1;
 196         M1 = R5;
 197         R6 = B2;
 198         M2 = R6;
 199         R7 = B3;
 200         M3 = R7;
 201
 202         R0 = M3;
 203         R1 = M2;
 204         R2 = M1;
 205         R3 = M0;
 206         R4 = I3;
 207         R5 = I2;
 208         R6 = I1;
 209         R7 = I0;
 210         CHECKREG r0, 0x1EEE1FFF;
 211         CHECKREG r1, 0x1CCC1DDD;
 212         CHECKREG r2, 0x1AAA1BBB;
 213         CHECKREG r3, 0x2EEE3FFF;
 214         CHECKREG r4, 0x26663777;
 215         CHECKREG r5, 0x24443555;
 216         CHECKREG r6, 0x22223333;
 217         CHECKREG r7, 0x20003111;
 218
 219         imm32 r0, 0x00000030;
 220         imm32 r1, 0x00000031;
 221         imm32 r2, 0x00000003;
 222         imm32 r3, 0x00330003;
 223         imm32 r4, 0x00440004;
 224         imm32 r5, 0x00550005;
 225         imm32 r6, 0x00660006;
 226         imm32 r7, 0x00770007;
 227
 228 // R-reg to R-reg to sysreg to Reg: no stall
 229         R3 = R0;
 230         ASTAT = R3;
 231         R6 = ASTAT;
 232         R4 = R1;
 233         RETS = R4;
 234         R7 = RETS;
 235
 236         CHECKREG r0, 0x00000030;
 237         CHECKREG r1, 0x00000031;
 238         CHECKREG r2, 0x00000003;
 239         CHECKREG r3, 0x00000030;
 240         CHECKREG r4, 0x00000031;
 241         CHECKREG r5, 0x00550005;
 242         CHECKREG r6, 0x00000030;
 243         CHECKREG r7, 0x00000031;
 244
 245         pass