sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s

   1 //Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp
   2 // Spec Reference: regmv dreg-acc-acc
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 // check R-reg to ACC
  11         imm32 r0, 0x00000000;
  12         imm32 r1, 0x12345678;
  13         imm32 r2, 0x91234567;
  14         imm32 r3, 0x00060007;
  15         imm32 r4, 0x00080009;
  16         imm32 r5, 0x000a000b;
  17         imm32 r6, 0x000c000d;
  18         imm32 r7, 0x000e000f;
  19         A0 = R0;
  20         A1 = R0;
  21         A0 = R1;
  22         A1 = R2;
  23
  24         R3 = A0.w;
  25         R4 = A0.x;
  26         R5 = A1.w;
  27         R6 = A1.x;
  28         CHECKREG r0, 0x00000000;
  29         CHECKREG r1, 0x12345678;
  30         CHECKREG r2, 0x91234567;
  31         CHECKREG r3, 0x12345678;
  32         CHECKREG r4, 0x00000000;
  33         CHECKREG r5, 0x91234567;
  34         CHECKREG r6, 0xFFFFFFFF;
  35         CHECKREG r7, 0x000E000F;
  36
  37         A1 = A0 = 0;
  38         R3 = A0.w;
  39         R4 = A0.x;
  40         R5 = A1.w;
  41         R6 = A1.x;
  42         CHECKREG r3, 0x00000000;
  43         CHECKREG r4, 0x00000000;
  44         CHECKREG r5, 0x00000000;
  45         CHECKREG r6, 0x00000000;
  46
  47         imm32 r0, 0xa5678901;
  48         imm32 r1, 0xb0158978;
  49         imm32 r2, 0x91234567;
  50         imm32 r3, 0x10060007;
  51         imm32 r4, 0x02080009;
  52         imm32 r5, 0x003a000b;
  53         imm32 r6, 0x0004000d;
  54         imm32 r7, 0x000e500f;
  55         A0 = R0;
  56         A1 = R1;
  57
  58         R3 = A0.w;
  59         R4 = A0.x;
  60         R5 = A1.w;
  61         R6 = A1.x;
  62         CHECKREG r0, 0xA5678901;
  63         CHECKREG r1, 0xB0158978;
  64         CHECKREG r2, 0x91234567;
  65         CHECKREG r3, 0xA5678901;
  66         CHECKREG r4, 0xFFFFFFFF;
  67         CHECKREG r5, 0xB0158978;
  68         CHECKREG r6, 0xFFFFFFFF;
  69         CHECKREG r7, 0x000E500F;
  70
  71         imm32 r0, 0xe9627911;
  72         imm32 r1, 0xd0158978;
  73         imm32 r2, 0xc1234567;
  74         imm32 r3, 0x10060007;
  75         imm32 r4, 0x02080009;
  76         imm32 r5, 0x003a000b;
  77         imm32 r6, 0x0004000d;
  78         imm32 r7, 0x000e500f;
  79         A0 = R0;
  80         A1 = A0;
  81
  82         imm32 r0, 0x90ba7911;
  83         imm32 r1, 0xe3458978;
  84         imm32 r2, 0xc1234567;
  85         imm32 r3, 0x10060007;
  86         imm32 r4, 0x56080009;
  87         imm32 r5, 0x783a000b;
  88         imm32 r6, 0xf247890d;
  89         imm32 r7, 0x489e534f;
  90         A0.w = R0;
  91         A0.x = R1;
  92         A1.w = R2;
  93         A1.x = R3;
  94
  95         R4 = A0.w;
  96         R5 = A0.x;
  97         R6 = A1.w;
  98         R7 = A1.x;
  99
 100         CHECKREG r0, 0x90BA7911;
 101         CHECKREG r1, 0xE3458978;
 102         CHECKREG r2, 0xC1234567;
 103         CHECKREG r3, 0x10060007;
 104         CHECKREG r4, 0x90BA7911;
 105         CHECKREG r5, 0x00000078;
 106         CHECKREG r6, 0xC1234567;
 107         CHECKREG r7, 0x00000007;
 108
 109         R3 = A0.w;
 110         R4 = A0.x;
 111         R5 = A1.w;
 112         R6 = A1.x;
 113         CHECKREG r0, 0x90BA7911;
 114         CHECKREG r1, 0xE3458978;
 115         CHECKREG r2, 0xC1234567;
 116         CHECKREG r3, 0x90BA7911;
 117         CHECKREG r4, 0x00000078;
 118         CHECKREG r5, 0xC1234567;
 119         CHECKREG r6, 0x00000007;
 120         CHECKREG r7, 0x00000007;
 121
 122         imm32 r0, 0xf9627911;
 123         imm32 r1, 0xd0158978;
 124         imm32 r2, 0xc1234567;
 125         imm32 r3, 0x10060007;
 126         imm32 r4, 0x02080009;
 127         imm32 r5, 0x003a000b;
 128         imm32 r6, 0xf247890d;
 129         imm32 r7, 0x789e534f;
 130         A0 = R6;
 131         A1.w = A0.w;
 132         A1.x = A0.x;
 133
 134         R0 = A0.w;
 135         R1 = A0.x;
 136         R2 = A1.w;
 137         R3 = A1.x;
 138
 139         A1 = R7;
 140         A0.w = A1.w;
 141         A0.x = A1.x;
 142
 143         R4 = A0.w;
 144         R5 = A0.x;
 145         R6 = A1.w;
 146         R7 = A1.x;
 147
 148         CHECKREG r0, 0xF247890D;
 149         CHECKREG r1, 0xFFFFFFFF;
 150         CHECKREG r2, 0xF247890D;
 151         CHECKREG r3, 0xFFFFFFFF;
 152         CHECKREG r4, 0x789E534F;
 153         CHECKREG r5, 0x00000000;
 154         CHECKREG r6, 0x789E534F;
 155         CHECKREG r7, 0x00000000;
 156
 157         imm32 r0, 0x90ba7911;
 158         imm32 r1, 0xe3458978;
 159         imm32 r2, 0xc1234567;
 160         imm32 r3, 0x10060007;
 161         imm32 r4, 0x56080009;
 162         imm32 r5, 0x783a000b;
 163         imm32 r6, 0xf247890d;
 164         imm32 r7, 0x489e534f;
 165         A0.w = A1.x;
 166         A0.x = A1.x;
 167         R4 = A0.w;
 168         R5 = A0.x;
 169
 170         A0 = R2;
 171         A1.w = A0.x;
 172         A1.x = A0.x;
 173
 174         R6 = A1.w;
 175         R7 = A1.x;
 176
 177         A0.x = A1.w;
 178         A1.x = A0.w;
 179         R0 = A0.x;
 180         R1 = A1.x;
 181
 182         CHECKREG r0, 0xFFFFFFFF;
 183         CHECKREG r1, 0x00000067;
 184         CHECKREG r2, 0xC1234567;
 185         CHECKREG r3, 0x10060007;
 186         CHECKREG r4, 0x00000000;
 187         CHECKREG r5, 0x00000000;
 188         CHECKREG r6, 0xFFFFFFFF;
 189         CHECKREG r7, 0xFFFFFFFF;
 190
 191         pass