Add support to GDB for the Renesas rl78 architecture.
[external/binutils.git] / sim / testsuite / sim / bfin / c_pushpopmultiple_dp.s
1 //Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp
2 // Spec Reference: pushpopmultiple dreg preg single group
3 # mach: bfin
4
5 .include "testutils.inc"
6         start
7
8         FP = SP;
9
10         imm32 r0, 0x00000000;
11         ASTAT = r0;
12
13         R0 = 0x01;
14         R1 = 0x02;
15         R2 = 0x03;
16         R3 = 0x04;
17         R4 = 0x05;
18         R5 = 0x06;
19         R6 = 0x07;
20         R7 = 0x08;
21
22         P1 = 0xa1 (X);
23         P2 = 0xa2 (X);
24         P3 = 0xa3 (X);
25         P4 = 0xa4 (X);
26         P5 = 0xa5 (X);
27         [ -- SP ] = ( R7:0 );
28         [ -- SP ] = ( P5:1 );
29
30         R1 = 0x12;
31         R2 = 0x13;
32         R3 = 0x14;
33         R4 = 0x15;
34         R5 = 0x16;
35         R6 = 0x17;
36         R7 = 0x18;
37
38         P2 = 0xb2 (X);
39         P3 = 0xb3 (X);
40         P4 = 0xb4 (X);
41         P5 = 0xb5 (X);
42         [ -- SP ] = ( R7:1 );
43         [ -- SP ] = ( P5:2 );
44
45         R2 = 0x23;
46         R3 = 0x24;
47         R4 = 0x25;
48         R5 = 0x26;
49         R6 = 0x27;
50         R7 = 0x28;
51
52         P3 = 0xc3 (X);
53         P4 = 0xc4 (X);
54         P5 = 0xc5 (X);
55         [ -- SP ] = ( R7:2 );
56         [ -- SP ] = ( P5:3 );
57
58         R3 = 0x34;
59         R4 = 0x35;
60         R5 = 0x36;
61         R6 = 0x37;
62         R7 = 0x38;
63
64         P4 = 0xd4 (X);
65         P5 = 0xd5 (X);
66         [ -- SP ] = ( R7:3 );
67         [ -- SP ] = ( P5:4 );
68
69         R4 = 0x45 (X);
70         R5 = 0x46 (X);
71         R6 = 0x47 (X);
72         R7 = 0x48 (X);
73         P5 = 0xe5 (X);
74         [ -- SP ] = ( R7:4 );
75         [ -- SP ] = ( P5:5 );
76
77         R5 = 0x56 (X);
78         R6 = 0x57 (X);
79         R7 = 0x58 (X);
80         [ -- SP ] = ( R7:5 );
81         R6 = 0x67 (X);
82         R7 = 0x68 (X);
83         [ -- SP ] = ( R7:6 );
84         R7 = 0x78 (X);
85         [ -- SP ] = ( R7:7 );
86         R0 = 0;
87         R1 = 0;
88         R2 = 0;
89         R3 = 0;
90         R4 = 0;
91         R5 = 0;
92         R6 = 0;
93         R7 = 0;
94         P1 = 0;
95         P2 = 0;
96         P3 = 0;
97         P4 = 0;
98         P5 = 0;
99         ( R7:7 ) = [ SP ++ ];
100         CHECKREG r0, 0x00000000;
101         CHECKREG r1, 0x00000000;
102         CHECKREG r2, 0x00000000;
103         CHECKREG r3, 0x00000000;
104         CHECKREG r4, 0x00000000;
105         CHECKREG r5, 0x00000000;
106         CHECKREG r6, 0x00000000;
107         CHECKREG r7, 0x00000078;
108
109         ( R7:6 ) = [ SP ++ ];
110         CHECKREG r0, 0x00000000;
111         CHECKREG r1, 0x00000000;
112         CHECKREG r2, 0x00000000;
113         CHECKREG r3, 0x00000000;
114         CHECKREG r4, 0x00000000;
115         CHECKREG r5, 0x00000000;
116         CHECKREG r6, 0x00000067;
117         CHECKREG r7, 0x00000068;
118
119         ( R7:5 ) = [ SP ++ ];
120         CHECKREG r0, 0x00000000;
121         CHECKREG r1, 0x00000000;
122         CHECKREG r2, 0x00000000;
123         CHECKREG r3, 0x00000000;
124         CHECKREG r4, 0x00000000;
125         CHECKREG r5, 0x00000056;
126         CHECKREG r6, 0x00000057;
127         CHECKREG r7, 0x00000058;
128
129         ( P5:5 ) = [ SP ++ ];
130         ( R7:4 ) = [ SP ++ ];
131         CHECKREG p1, 0x00000000;
132         CHECKREG p2, 0x00000000;
133         CHECKREG p3, 0x00000000;
134         CHECKREG p4, 0x00000000;
135         CHECKREG p5, 0x000000e5;
136
137         CHECKREG r0, 0x00000000;
138         CHECKREG r1, 0x00000000;
139         CHECKREG r2, 0x00000000;
140         CHECKREG r3, 0x00000000;
141         CHECKREG r4, 0x00000045;
142         CHECKREG r5, 0x00000046;
143         CHECKREG r6, 0x00000047;
144         CHECKREG r7, 0x00000048;
145
146         ( P5:4 ) = [ SP ++ ];
147         ( R7:3 ) = [ SP ++ ];
148         CHECKREG p1, 0x00000000;
149         CHECKREG p2, 0x00000000;
150         CHECKREG p3, 0x00000000;
151         CHECKREG p4, 0x000000d4;
152         CHECKREG p5, 0x000000d5;
153
154         CHECKREG r0, 0x00000000;
155         CHECKREG r1, 0x00000000;
156         CHECKREG r2, 0x00000000;
157         CHECKREG r3, 0x00000034;
158         CHECKREG r4, 0x00000035;
159         CHECKREG r5, 0x00000036;
160         CHECKREG r6, 0x00000037;
161         CHECKREG r7, 0x00000038;
162
163         ( P5:3 ) = [ SP ++ ];
164         ( R7:2 ) = [ SP ++ ];
165         CHECKREG p1, 0x00000000;
166         CHECKREG p2, 0x00000000;
167         CHECKREG p3, 0x000000c3;
168         CHECKREG p4, 0x000000c4;
169         CHECKREG p5, 0x000000c5;
170
171         CHECKREG r0, 0x00000000;
172         CHECKREG r1, 0x00000000;
173         CHECKREG r2, 0x00000023;
174         CHECKREG r3, 0x00000024;
175         CHECKREG r4, 0x00000025;
176         CHECKREG r5, 0x00000026;
177         CHECKREG r6, 0x00000027;
178         CHECKREG r7, 0x00000028;
179
180         ( P5:2 ) = [ SP ++ ];
181         ( R7:1 ) = [ SP ++ ];
182         CHECKREG p1, 0x00000000;
183         CHECKREG p2, 0x000000b2;
184         CHECKREG p3, 0x000000b3;
185         CHECKREG p4, 0x000000b4;
186         CHECKREG p5, 0x000000b5;
187
188         CHECKREG r0, 0x00000000;
189         CHECKREG r1, 0x00000012;
190         CHECKREG r2, 0x00000013;
191         CHECKREG r3, 0x00000014;
192         CHECKREG r4, 0x00000015;
193         CHECKREG r5, 0x00000016;
194         CHECKREG r6, 0x00000017;
195         CHECKREG r7, 0x00000018;
196
197         ( P5:1 ) = [ SP ++ ];
198         ( R7:0 ) = [ SP ++ ];
199         CHECKREG p1, 0x000000a1;
200         CHECKREG p2, 0x000000a2;
201         CHECKREG p3, 0x000000a3;
202         CHECKREG p4, 0x000000a4;
203         CHECKREG p5, 0x000000a5;
204
205         CHECKREG r0, 0x00000001;
206         CHECKREG r1, 0x00000002;
207         CHECKREG r2, 0x00000003;
208         CHECKREG r3, 0x00000004;
209         CHECKREG r4, 0x00000005;
210         CHECKREG r5, 0x00000006;
211         CHECKREG r6, 0x00000007;
212         CHECKREG r7, 0x00000008;
213         pass