sim/testsuite/sim/bfin/c_loopsetup_nested_prelc.s

   1 //Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp
   2 // Spec Reference: loopsetup nested preload lc0 lc1
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS 0;
  10
  11 ASTAT = r0;
  12
  13 //p0 = 2;
  14 P1 = 3;
  15 P2 = 4;
  16 P3 = 5;
  17 P4 = 6;
  18 P5 = 7;
  19 SP = 8;
  20 FP = 9;
  21
  22 R0 = 0x05;
  23 R1 = 0x10;
  24 R2 = 0x12;
  25 R3 = 0x14;
  26 R4 = 0x18;
  27 R5 = 0x16;
  28 R6 = 0x16;
  29 R7 = 0x18;
  30
  31 LC0 = R0;
  32 LC1 = R1;
  33 LSETUP ( start1 , end1 ) LC0;
  34 start1: R0 += 1;
  35  R1 += -2;
  36 LSETUP ( start2 , end2 ) LC1;
  37 start2: R4 += 4;
  38 end2: R5 += -5;
  39  R3 += 1;
  40 end1: R2 += 3;
  41  R3 += 4;
  42 LC0 = R7;
  43 LC1 = R6;
  44 LSETUP ( start3 , end3 ) LC0;
  45 start3: R6 += 6;
  46 LSETUP ( start4 , end4 ) LC1;
  47 start4: R0 += 1;
  48  R1 += -2;
  49 end4: R2 += 3;
  50  R3 += 4;
  51 end3: R7 += -7;
  52  R3 += 1;
  53 CHECKREG r0, 0x00000037;
  54 CHECKREG r1, 0xFFFFFFAC;
  55 CHECKREG r2, 0x000000A8;
  56 CHECKREG r3, 0x0000007E;
  57 CHECKREG r4, 0x00000068;
  58 CHECKREG r5, 0xFFFFFFB2;
  59 CHECKREG r6, 0x000000A6;
  60 CHECKREG r7, 0xFFFFFF70;
  61
  62 R0 = 0x05;
  63 R1 = 0x10;
  64 R2 = 0x08;
  65 R3 = 0x0C;
  66 R4 = 0x40 (X);
  67 R5 = 0x50 (X);
  68 R6 = 0x60 (X);
  69 R7 = 0x70 (X);
  70
  71 LC0 = R2;
  72 LC1 = R3;
  73 LSETUP ( start5 , end5 ) LC0;
  74 start5: R4 += 1;
  75 LSETUP ( start6 , end6 ) LC1;
  76 start6: R6 += 4;
  77 end6: R7 += -5;
  78  R3 += 6;
  79 end5: R5 += -2;
  80  R3 += 3;
  81 CHECKREG r0, 0x00000005;
  82 CHECKREG r1, 0x00000010;
  83 CHECKREG r2, 0x00000008;
  84 CHECKREG r3, 0x0000003F;
  85 CHECKREG r4, 0x00000048;
  86 CHECKREG r5, 0x00000040;
  87 CHECKREG r6, 0x000000AC;
  88 CHECKREG r7, 0x00000011;
  89 LSETUP ( start7 , end7 ) LC0;
  90 start7: R4 += 4;
  91 end7: R5 += -5;
  92  R3 += 6;
  93 CHECKREG r0, 0x00000005;
  94 CHECKREG r1, 0x00000010;
  95 CHECKREG r2, 0x00000008;
  96 CHECKREG r3, 0x00000045;
  97 CHECKREG r4, 0x0000004C;
  98 CHECKREG r5, 0x0000003B;
  99 CHECKREG r6, 0x000000AC;
 100 CHECKREG r7, 0x00000011;
 101
 102 P1 = 12;
 103 P2 = 14;
 104 P3 = 16;
 105 P4 = 18;
 106 P5 = 12;
 107 SP = 14;
 108 FP = 16;
 109
 110 R0 = 0x05;
 111 R1 = 0x10;
 112 R2 = 0x14;
 113 R3 = 0x18;
 114 R4 = 0x16;
 115 R5 = 0x04;
 116 R6 = 0x30;
 117 R7 = 0x30;
 118
 119 LC0 = R5;
 120 LC1 = R4;
 121 LSETUP ( start11 , end11 ) LC0;
 122 start11: R0 += 1;
 123  R1 += -1;
 124 LSETUP ( start15 , end15 ) LC1;
 125 start15: R4 += 1;
 126 end15: R5 += -1;
 127  R3 += 1;
 128 end11: R2 += 1;
 129  R3 += 1;
 130
 131
 132 LSETUP ( start13 , end13 ) LC0 = P5;
 133 start13: R6 += 1;
 134 LSETUP ( start12 , end12 ) LC1 = P2;
 135 start12: R4 += 1;
 136 end12: R5 += -1;
 137  R3 += 1;
 138 end13: R7 += -1;
 139  R3 += 1;
 140 CHECKREG r0, 0x00000009;
 141 CHECKREG r1, 0x0000000C;
 142 CHECKREG r2, 0x00000018;
 143 CHECKREG r3, 0x0000002A;
 144 CHECKREG r4, 0x000000D7;
 145 CHECKREG r5, 0xFFFFFF43;
 146 CHECKREG r6, 0x0000003C;
 147 CHECKREG r7, 0x00000024;
 148
 149 R0 = 0x05;
 150 R1 = 0x10;
 151 R2 = 0x20;
 152 R3 = 0x30;
 153 R4 = 0x40 (X);
 154 R5 = 0x50 (X);
 155 R6 = 0x14;
 156 R7 = 0x08;
 157 P4 = 6;
 158 FP = 8;
 159
 160 LC0 = R6;
 161 LC1 = R7;
 162 LSETUP ( start14 , end14 ) LC0 = P4;
 163 start14: R0 += 1;
 164  R1 += -1;
 165 LSETUP ( start16 , end16 ) LC1;
 166 start16: R6 += 1;
 167 end16: R7 += -1;
 168  R3 += 1;
 169 LSETUP ( start17 , end17 ) LC1 = FP >> 1;
 170 start17: R4 += 1;
 171 end17: R5 += -1;
 172  R3 += 1;
 173 end14: R2 += 1;
 174  R3 += 1;
 175 CHECKREG r0, 0x0000000B;
 176 CHECKREG r1, 0x0000000A;
 177 CHECKREG r2, 0x00000026;
 178 CHECKREG r3, 0x0000003D;
 179 CHECKREG r4, 0x00000058;
 180 CHECKREG r5, 0x00000038;
 181 CHECKREG r6, 0x00000021;
 182 CHECKREG r7, 0xFFFFFFFB;
 183
 184 pass