1 //Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp
2 // Spec Reference: c_ldstii store dreg
5 .include "testutils.inc"
17 loadsym p1, DATA_ADDR_1;
18 loadsym p2, DATA_ADDR_2;
20 loadsym p3, DATA_ADDR_3;
22 loadsym p4, DATA_ADDR_4;
23 loadsym p5, DATA_ADDR_1;
24 loadsym fp, DATA_ADDR_2;
26 loadsym sp, DATA_ADDR_3;
45 CHECKREG r0, 0x7019B0A6;
46 CHECKREG r1, 0xD028C0A7;
47 CHECKREG r2, 0x501B90A4;
48 CHECKREG r3, 0x402C80A3;
49 CHECKREG r4, 0x300370A2;
50 CHECKREG r5, 0x204E60A1;
51 CHECKREG r6, 0x105F50A0;
52 CHECKREG r7, 0x600AA0A5;
79 CHECKREG r0, 0x30BD70B2;
80 CHECKREG r1, 0x40BC80B3;
81 CHECKREG r2, 0x55BB90B4;
82 CHECKREG r3, 0x10BF50B0;
83 CHECKREG r4, 0x20BE60B1;
84 CHECKREG r5, 0x60BAA0B5;
85 CHECKREG r6, 0x70B9B0B6;
86 CHECKREG r7, 0x80B8C0B7;
117 CHECKREG r0, 0x60CAA0C5;
118 CHECKREG r1, 0xD0C8C0C7;
119 CHECKREG r2, 0x50CB90C4;
121 CHECKREG r3, 0x40CC80C3;
122 CHECKREG r4, 0x30C370C2;
123 CHECKREG r5, 0x20CE60C1;
124 CHECKREG r6, 0x10CF50C0;
127 imm32 r0, 0x60df50d0;
128 imm32 r1, 0x70de60d1;
129 imm32 r2, 0x80dd70d2;
130 imm32 r3, 0x90dc80d3;
131 imm32 r4, 0xa0db90d4;
132 imm32 r5, 0xb0daa0d5;
133 imm32 r6, 0xc0d9b0d6;
134 imm32 r7, 0xd0d8c0d7;
151 CHECKREG r0, 0x80DD70D2;
152 CHECKREG r1, 0x90DC80D3;
153 CHECKREG r2, 0xA0DB90D4;
154 CHECKREG r3, 0x60DF50D0;
155 CHECKREG r4, 0x70DE60D1;
156 CHECKREG r5, 0xB0DAA0D5;
157 CHECKREG r6, 0xC0D9B0D6;
158 CHECKREG r7, 0xD0D8C0D7;
162 // Pre-load memory with known data
163 // More data is defined than will actually be used