1 //Original:testcases/core/c_ldstii_ld_dreg/c_ldstii_ld_dreg.dsp
2 // Spec Reference: c_ldstii load dreg
5 .include "testutils.inc"
18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
19 loadsym p1, DATA_ADDR_1, 0x00;
20 loadsym p2, DATA_ADDR_2, 0x04;
21 loadsym i1, DATA_ADDR_3, 0x04;
22 loadsym p4, DATA_ADDR_1, 0x00;
23 loadsym p5, DATA_ADDR_2, 0x00;
24 loadsym fp, DATA_ADDR_3, 0x00;
25 loadsym i3, DATA_ADDR_4, 0x00;
35 CHECKREG r0, 0x00010203;
36 CHECKREG r1, 0x04050607;
37 CHECKREG r2, 0x08090A0B;
38 CHECKREG r3, 0x0C0D0E0F;
39 CHECKREG r4, 0x10111213;
40 CHECKREG r5, 0x14151617;
41 CHECKREG r6, 0x18191A1B;
50 CHECKREG r0, 0x91929394;
51 CHECKREG r1, 0x95969798;
52 CHECKREG r2, 0x99A1A2A3;
53 CHECKREG r3, 0xA5A6A7A8;
54 CHECKREG r4, 0xA9B0B1B2;
55 CHECKREG r5, 0xB3B4B5B6;
56 CHECKREG r6, 0xB7B8B9C0;
65 CHECKREG r0, 0x91E899EA;
66 CHECKREG r1, 0x92E899EA;
67 CHECKREG r2, 0x93E899EA;
68 CHECKREG r3, 0x92E899EA;
69 CHECKREG r4, 0x91E899EA;
70 CHECKREG r5, 0xE3E4E5E6;
71 CHECKREG r6, 0xDFE0E1E2;
80 CHECKREG r0, 0x74757677;
81 CHECKREG r1, 0x99717273;
82 CHECKREG r2, 0x55667788;
83 CHECKREG r3, 0x11223344;
84 CHECKREG r4, 0x1C1D1E1F;
85 CHECKREG r5, 0x18191A1B;
86 CHECKREG r6, 0x14151617;
95 CHECKREG r0, 0x30313233;
96 CHECKREG r1, 0x2C2D2E2F;
97 CHECKREG r2, 0x28292A2B;
98 CHECKREG r3, 0x24252627;
99 CHECKREG r4, 0x20212223;
100 CHECKREG r5, 0x24252627;
101 CHECKREG r6, 0x28292A2B;
110 CHECKREG r0, 0x4C4D4E4F;
111 CHECKREG r1, 0x50515253;
112 CHECKREG r2, 0x54555657;
113 CHECKREG r3, 0x58595A5B;
114 CHECKREG r4, 0xC5C6C7C8;
115 CHECKREG r5, 0xC9CACBCD;
116 CHECKREG r6, 0xCFD0D1D2;
125 CHECKREG r0, 0xF7F8F9FA;
126 CHECKREG r1, 0xFBFCFDFE;
127 CHECKREG r2, 0xFF000102;
128 CHECKREG r3, 0x03040506;
129 CHECKREG r4, 0x0708090A;
130 CHECKREG r5, 0x0B0CAD0E;
131 CHECKREG r6, 0xAB0CAD01;
136 // Pre-load memory with known data
137 // More data is defined than will actually be used