1 //Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp
2 // Spec Reference: c_ldstii load dreg xh
5 .include "testutils.inc"
19 I1 = P3; P3 = I0; I3 = SP; SP = I2;
20 loadsym p1, DATA_ADDR_1, 0x00;
21 loadsym p2, DATA_ADDR_2, 0x04;
22 loadsym i1, DATA_ADDR_3, 0x04;
23 loadsym p4, DATA_ADDR_1, 0x00;
24 loadsym p5, DATA_ADDR_2, 0x00;
25 loadsym fp, DATA_ADDR_3, 0x00;
26 loadsym i3, DATA_ADDR_4, 0x00;
29 R0 = W [ P1 + 0 ] (X);
30 R1 = W [ P1 + 4 ] (X);
31 R2 = W [ P1 + 8 ] (X);
32 R3 = W [ P1 + 12 ] (X);
33 R4 = W [ P1 + 16 ] (X);
34 R5 = W [ P1 + 20 ] (X);
35 R6 = W [ P1 + 24 ] (X);
36 CHECKREG r0, 0x00000203;
37 CHECKREG r1, 0x00000607;
38 CHECKREG r2, 0x00000A0B;
39 CHECKREG r3, 0x00000E0F;
40 CHECKREG r4, 0x00001213;
41 CHECKREG r5, 0x00001617;
42 CHECKREG r6, 0x00001A1B;
44 R0 = W [ P2 + 28 ] (X);
45 R1 = W [ P2 + 32 ] (X);
46 R2 = W [ P2 + 36 ] (X);
47 R3 = W [ P2 + 40 ] (X);
48 R4 = W [ P2 + 44 ] (X);
49 R5 = W [ P2 + 48 ] (X);
50 R6 = W [ P2 + 52 ] (X);
51 CHECKREG r0, 0xFFFF9394;
52 CHECKREG r1, 0xFFFF9798;
53 CHECKREG r2, 0xFFFFA2A3;
54 CHECKREG r3, 0xFFFFA7A8;
55 CHECKREG r4, 0xFFFFB1B2;
56 CHECKREG r5, 0xFFFFB5B6;
57 CHECKREG r6, 0xFFFFB9C0;
59 R0 = W [ P3 + 56 ] (X);
60 R1 = W [ P3 + 60 ] (X);
61 R2 = W [ P3 + 64 ] (X);
62 R3 = W [ P3 + 60 ] (X);
63 R4 = W [ P3 + 56 ] (X);
64 R5 = W [ P3 + 52 ] (X);
65 R6 = W [ P3 + 48 ] (X);
66 CHECKREG r0, 0xFFFF99EA;
67 CHECKREG r1, 0xFFFF99EA;
68 CHECKREG r2, 0xFFFF99EA;
69 CHECKREG r3, 0xFFFF99EA;
70 CHECKREG r4, 0xFFFF99EA;
71 CHECKREG r5, 0xFFFFE5E6;
72 CHECKREG r6, 0xFFFFE1E2;
74 R0 = W [ P4 + 44 ] (X);
75 R1 = W [ P4 + 40 ] (X);
76 R2 = W [ P4 + 36 ] (X);
77 R3 = W [ P4 + 32 ] (X);
78 R4 = W [ P4 + 28 ] (X);
79 R5 = W [ P4 + 24 ] (X);
80 R6 = W [ P4 + 20 ] (X);
81 CHECKREG r0, 0x00007677;
82 CHECKREG r1, 0x00007273;
83 CHECKREG r2, 0x00007788;
84 CHECKREG r3, 0x00003344;
85 CHECKREG r4, 0x00001E1F;
86 CHECKREG r5, 0x00001A1B;
87 CHECKREG r6, 0x00001617;
89 R0 = W [ P5 + 16 ] (X);
90 R1 = W [ P5 + 12 ] (X);
91 R2 = W [ P5 + 8 ] (X);
92 R3 = W [ P5 + 4 ] (X);
93 R4 = W [ P5 + 0 ] (X);
94 R5 = W [ P5 + 4 ] (X);
95 R6 = W [ P5 + 8 ] (X);
96 CHECKREG r0, 0x00003233;
97 CHECKREG r1, 0x00002E2F;
98 CHECKREG r2, 0x00002A2B;
99 CHECKREG r3, 0x00002627;
100 CHECKREG r4, 0x00002223;
101 CHECKREG r5, 0x00002627;
102 CHECKREG r6, 0x00002A2B;
104 R0 = W [ FP + 12 ] (X);
105 R1 = W [ FP + 16 ] (X);
106 R2 = W [ FP + 20 ] (X);
107 R3 = W [ FP + 24 ] (X);
108 R4 = W [ FP + 28 ] (X);
109 R5 = W [ FP + 32 ] (X);
110 R6 = W [ FP + 36 ] (X);
111 CHECKREG r0, 0x00004E4F;
112 CHECKREG r1, 0x00005253;
113 CHECKREG r2, 0x00005657;
114 CHECKREG r3, 0x00005A5B;
115 CHECKREG r4, 0xFFFFC7C8;
116 CHECKREG r5, 0xFFFFCBCD;
117 CHECKREG r6, 0xFFFFD1D2;
119 R0 = W [ SP + 40 ] (X);
120 R1 = W [ SP + 44 ] (X);
121 R2 = W [ SP + 48 ] (X);
122 R3 = W [ SP + 52 ] (X);
123 R4 = W [ SP + 56 ] (X);
124 R5 = W [ SP + 60 ] (X);
125 R6 = W [ SP + 64 ] (X);
126 CHECKREG r0, 0xFFFFF9FA;
127 CHECKREG r1, 0xFFFFFDFE;
128 CHECKREG r2, 0x00000102;
129 CHECKREG r3, 0x00000506;
130 CHECKREG r4, 0x0000090A;
131 CHECKREG r5, 0xFFFFAD0E;
132 CHECKREG r6, 0xFFFFAD01;
137 // Pre-load memory with known data
138 // More data is defined than will actually be used