1 //Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp
2 // Spec Reference: c_ldstidxl store dreg
5 .include "testutils.inc"
26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
27 loadsym p1, DATA_ADDR_1, 0x00;
28 loadsym p2, DATA_ADDR_2, 0xc8;
29 loadsym i1, DATA_ADDR_1, 0x10;
30 loadsym p4, DATA_ADDR_2, 0xc8;
31 loadsym p5, DATA_ADDR_1, 0x00;
32 loadsym fp, DATA_ADDR_2, 0xc8;
33 loadsym i3, DATA_ADDR_1, 0x00;
36 B [ P1 + 0x1101 ] = R0;
37 B [ P1 + 0x1013 ] = R1;
38 B [ P1 + 0x1015 ] = R2;
39 B [ P1 + 0x1007 ] = R3;
40 B [ P2 + -0x1019 ] = R4;
41 B [ P2 + -0x1011 ] = R5;
42 B [ P2 + -0x1013 ] = R6;
43 B [ P2 + -0x1015 ] = R7;
44 R6 = B [ P1 + 0x1101 ] (Z);
45 R5 = B [ P1 + 0x1013 ] (Z);
46 R4 = B [ P1 + 0x1015 ] (Z);
47 R3 = B [ P1 + 0x1007 ] (Z);
48 R2 = B [ P2 + -0x1019 ] (Z);
49 R7 = B [ P2 + -0x1011 ] (Z);
50 R0 = B [ P2 + -0x1013 ] (Z);
51 R1 = B [ P2 + -0x1015 ] (Z);
52 CHECKREG r0, 0x000000E6;
53 CHECKREG r1, 0x000000F7;
54 CHECKREG r2, 0x000000C4;
55 CHECKREG r3, 0x000000B3;
56 CHECKREG r4, 0x000000A2;
57 CHECKREG r5, 0x00000091;
58 CHECKREG r6, 0x00000080;
59 CHECKREG r7, 0x000000D5;
69 B [ P3 + 0x1011 ] = R0;
70 B [ P3 + 0x1023 ] = R1;
71 B [ P3 + 0x1025 ] = R2;
72 B [ P3 + 0x1027 ] = R3;
73 B [ P4 + -0x1029 ] = R4;
74 B [ P4 + -0x1021 ] = R5;
75 B [ P4 + -0x1033 ] = R6;
76 B [ P4 + -0x1035 ] = R7;
77 R3 = B [ P3 + 0x1011 ] (Z);
78 R4 = B [ P3 + 0x1023 ] (Z);
79 R0 = B [ P3 + 0x1025 ] (Z);
80 R1 = B [ P3 + 0x1027 ] (Z);
81 R2 = B [ P4 + -0x1029 ] (Z);
82 R5 = B [ P4 + -0x1021 ] (Z);
83 R6 = B [ P4 + -0x1033 ] (Z);
84 R7 = B [ P4 + -0x1035 ] (Z);
85 CHECKREG r0, 0x000000B2;
86 CHECKREG r1, 0x000000B3;
87 CHECKREG r2, 0x000000B4;
88 CHECKREG r3, 0x000000B0;
89 CHECKREG r4, 0x000000B1;
90 CHECKREG r5, 0x000000B5;
91 CHECKREG r6, 0x000000B6;
92 CHECKREG r7, 0x000000B7;
100 imm32 r5, 0x60caa0c5;
101 imm32 r6, 0x70c9b0c6;
102 imm32 r7, 0xd0c8c0c7;
103 B [ P5 + 0x1031 ] = R0;
104 B [ P5 + 0x1033 ] = R1;
105 B [ P5 + 0x1035 ] = R2;
106 B [ P5 + 0x1047 ] = R3;
107 B [ SP + -0x1049 ] = R4;
108 B [ SP + -0x1041 ] = R5;
109 B [ SP + -0x1043 ] = R6;
110 B [ SP + -0x1045 ] = R7;
111 R6 = B [ P5 + 0x1031 ] (Z);
112 R5 = B [ P5 + 0x1033 ] (Z);
113 R4 = B [ P5 + 0x1035 ] (Z);
114 R3 = B [ P5 + 0x1047 ] (Z);
115 R2 = B [ SP + -0x1049 ] (Z);
116 R0 = B [ SP + -0x1041 ] (Z);
117 R7 = B [ SP + -0x1043 ] (Z);
118 R1 = B [ SP + -0x1045 ] (Z);
119 CHECKREG r0, 0x000000C5;
120 CHECKREG r1, 0x000000C7;
121 CHECKREG r2, 0x000000C4;
122 CHECKREG r3, 0x000000C3;
123 CHECKREG r4, 0x000000C2;
124 CHECKREG r5, 0x000000C1;
125 CHECKREG r6, 0x000000C0;
128 imm32 r0, 0x60df50d0;
129 imm32 r1, 0x70de60d1;
130 imm32 r2, 0x80dd70d2;
131 imm32 r3, 0x90dc80d3;
132 imm32 r4, 0xa0db90d4;
133 imm32 r5, 0xb0daa0d5;
134 imm32 r6, 0xc0d9b0d6;
135 imm32 r7, 0xd0d8c0d7;
136 B [ FP + 0x1051 ] = R0;
137 B [ FP + 0x1053 ] = R1;
138 B [ FP + 0x1055 ] = R2;
139 B [ FP + 0x1057 ] = R3;
140 B [ FP + 0x1059 ] = R4;
141 B [ FP + 0x1061 ] = R5;
142 B [ FP + 0x1063 ] = R6;
143 B [ FP + 0x1065 ] = R7;
144 R3 = B [ FP + 0x1051 ] (Z);
145 R4 = B [ FP + 0x1053 ] (Z);
146 R0 = B [ FP + 0x1055 ] (Z);
147 R1 = B [ FP + 0x1057 ] (Z);
148 R2 = B [ FP + 0x1059 ] (Z);
149 R5 = B [ FP + 0x1061 ] (Z);
150 R6 = B [ FP + 0x1063 ] (Z);
151 R7 = B [ FP + 0x1065 ] (Z);
152 CHECKREG r0, 0x000000D2;
153 CHECKREG r1, 0x000000D3;
154 CHECKREG r2, 0x000000D4;
155 CHECKREG r3, 0x000000D0;
156 CHECKREG r4, 0x000000D1;
157 CHECKREG r5, 0x000000D5;
158 CHECKREG r6, 0x000000D6;
159 CHECKREG r7, 0x000000D7;
164 // Pre-load memory witb known data
165 // More data is defined than will actually be used
168 // Make sure there is space between the text and data sections
611 // Make sure there is space for us to scribble