1 //Original:testcases/core/c_ldstidxl_ld_dr_b/c_ldstidxl_ld_dr_b.dsp
2 // Spec Reference: c_ldstidxl load dreg B (ld with indexed addressing)
5 .include "testutils.inc"
17 loadsym p1, DATA_ADDR_1, 0x00;
18 loadsym p2, DATA_ADDR_2, 0xA0;
19 loadsym p4, DATA_ADDR_2, 0x70;
20 loadsym p5, DATA_ADDR_1, 0x70;
21 loadsym fp, DATA_ADDR_2, 0x70;
23 R0 = B [ P1 + 151 ] (Z);
24 R1 = B [ P1 + 83 ] (Z);
25 R2 = B [ P1 + 45 ] (Z);
26 R3 = B [ P1 + 17 ] (Z);
27 R4 = B [ P1 + 39 ] (Z);
28 R5 = B [ P1 + 21 ] (Z);
29 R6 = B [ P1 + 123 ] (Z);
30 R7 = B [ P1 + 155 ] (Z);
31 CHECKREG r0, 0x00000000;
32 CHECKREG r1, 0x00000018;
33 CHECKREG r2, 0x00000076;
34 CHECKREG r3, 0x00000012;
35 CHECKREG r4, 0x00000055;
36 CHECKREG r5, 0x00000016;
37 CHECKREG r6, 0x00000058;
38 CHECKREG r7, 0x00000004;
40 R0 = B [ P2 + -121 ] (Z);
41 R1 = B [ P2 + -113 ] (Z);
42 R2 = B [ P2 + -35 ] (Z);
43 R3 = B [ P2 + -27 ] (Z);
44 R4 = B [ P2 + -49 ] (Z);
45 R5 = B [ P2 + -5 ] (Z);
46 R6 = B [ P2 + -51 ] (Z);
47 R7 = B [ P2 + -147 ] (Z);
48 CHECKREG r0, 0x000000CF;
49 CHECKREG r1, 0x000000D7;
50 CHECKREG r2, 0x00000056;
51 CHECKREG r3, 0x00000064;
52 CHECKREG r4, 0x00000094;
53 CHECKREG r5, 0x0000004C;
54 CHECKREG r6, 0x00000099;
55 CHECKREG r7, 0x0000004E;
57 R0 = B [ P4 + 47 ] (Z);
58 R1 = B [ P4 + -41 ] (Z);
59 R2 = B [ P4 + 38 ] (Z);
60 R3 = B [ P4 + -31 ] (Z);
61 R4 = B [ P4 + 28 ] (Z);
62 R5 = B [ P4 + 26 ] (Z);
63 R6 = B [ P4 + -22 ] (Z);
64 R7 = B [ P4 + 105 ] (Z);
65 CHECKREG r0, 0x00000050;
66 CHECKREG r1, 0x00000093;
67 CHECKREG r2, 0x00000049;
68 CHECKREG r3, 0x00000099;
69 CHECKREG r4, 0x00000043;
70 CHECKREG r5, 0x00000067;
71 CHECKREG r6, 0x000000E8;
72 CHECKREG r7, 0x00000099;
74 R0 = B [ P5 + -14 ] (Z);
75 R1 = B [ P5 + 12 ] (Z);
76 R2 = B [ P5 + -6 ] (Z);
77 R3 = B [ P5 + 4 ] (Z);
78 R4 = B [ P5 + 0 ] (Z);
79 R5 = B [ P5 + -2 ] (Z);
80 R6 = B [ P5 + 8 ] (Z);
81 R7 = B [ P5 + -107 ] (Z);
82 CHECKREG r0, 0x00000035;
83 CHECKREG r1, 0x00000065;
84 CHECKREG r2, 0x00000043;
85 CHECKREG r3, 0x00000057;
86 CHECKREG r4, 0x00000053;
87 CHECKREG r5, 0x00000047;
88 CHECKREG r6, 0x00000061;
89 CHECKREG r7, 0x00000006;
91 R0 = B [ FP + 99 ] (Z);
92 R1 = B [ FP + -15 ] (Z);
93 R2 = B [ FP + 41 ] (Z);
94 R3 = B [ FP + -65 ] (Z);
95 R4 = B [ FP + 25 ] (Z);
96 R5 = B [ FP + -34 ] (Z);
97 R6 = B [ FP + 37 ] (Z);
98 R7 = B [ FP + -97 ] (Z);
99 CHECKREG r0, 0x00000093;
100 CHECKREG r1, 0x00000099;
101 CHECKREG r2, 0x0000004E;
102 CHECKREG r3, 0x000000D7;
103 CHECKREG r4, 0x00000068;
104 CHECKREG r5, 0x000000E8;
105 CHECKREG r6, 0x0000004A;
106 CHECKREG r7, 0x0000004C;
110 // Pre-load memory with known data
111 // More data is defined than will actually be used
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