1 //Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp
2 // Spec Reference: c_dspldst st_drhi_ipp
5 .include "testutils.inc"
15 // Half reg 16 bit mem store
27 loadsym i0, DATA_ADDR_3;
28 loadsym i1, DATA_ADDR_4;
29 loadsym i2, DATA_ADDR_5;
30 loadsym i3, DATA_ADDR_6;
50 loadsym i0, DATA_ADDR_3;
51 loadsym i1, DATA_ADDR_4;
52 loadsym i2, DATA_ADDR_5;
53 loadsym i3, DATA_ADDR_6;
62 CHECKREG r0, 0x11B10A12;
63 CHECKREG r1, 0x222C11B1;
64 CHECKREG r2, 0x3344222C;
65 CHECKREG r3, 0x55663344;
66 CHECKREG r4, 0x55663344;
67 CHECKREG r5, 0x789A5566;
68 CHECKREG r6, 0xABCD789A;
69 CHECKREG r7, 0x0123ABCD;
79 CHECKREG r0, 0x08090A0B;
80 CHECKREG r1, 0x28292A2B;
81 CHECKREG r2, 0x48494A4B;
82 CHECKREG r3, 0x68696A6B;
83 CHECKREG r4, 0x0C0D0E0F;
84 CHECKREG r5, 0x2C2D2E2F;
85 CHECKREG r6, 0x4C4D4E4F;
86 CHECKREG r7, 0x6C6D6E6F;
99 loadsym i0, DATA_ADDR_3, 0x20;
100 loadsym i1, DATA_ADDR_4, 0x20;
101 loadsym i2, DATA_ADDR_5, 0x20;
102 loadsym i3, DATA_ADDR_6, 0x20;
121 loadsym i0, DATA_ADDR_3, 0x20;
122 loadsym i1, DATA_ADDR_4, 0x20;
123 loadsym i2, DATA_ADDR_5, 0x20;
124 loadsym i3, DATA_ADDR_6, 0x20;
133 CHECKREG r0, 0x000001B2;
134 CHECKREG r1, 0x00001014;
135 CHECKREG r2, 0x0000A201;
136 CHECKREG r3, 0x0000BB30;
137 CHECKREG r4, 0x1014BB30;
138 CHECKREG r5, 0xA201DEC4;
139 CHECKREG r6, 0xBB305F7D;
140 CHECKREG r7, 0xDEC43089;
150 CHECKREG r0, 0xDEC41A1B;
151 CHECKREG r1, 0x5F7D3A3B;
152 CHECKREG r2, 0x30895A5B;
153 CHECKREG r3, 0x719A7A7B;
154 CHECKREG r4, 0x14151617;
155 CHECKREG r5, 0x34353637;
156 CHECKREG r6, 0x54555657;
157 CHECKREG r7, 0x74757677;
161 // Pre-load memory with known data
162 // More data is defined than will actually be used