1 //Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp
2 // Spec Reference: c_dspldst st_dr_ipp
5 .include "testutils.inc"
25 loadsym i0, DATA_ADDR_3;
26 loadsym i1, DATA_ADDR_4;
27 loadsym i2, DATA_ADDR_5;
28 loadsym i3, DATA_ADDR_6;
49 loadsym i0, DATA_ADDR_3;
50 loadsym i1, DATA_ADDR_4;
51 loadsym i2, DATA_ADDR_5;
52 loadsym i3, DATA_ADDR_6;
61 CHECKREG r0, 0x0a234507;
62 CHECKREG r1, 0x1b345618;
63 CHECKREG r2, 0x2c456729;
64 CHECKREG r3, 0x3d56783a;
65 CHECKREG r4, 0x1B345618;
66 CHECKREG r5, 0x2C456729;
67 CHECKREG r6, 0x3D56783A;
68 CHECKREG r7, 0x4E67894B;
77 CHECKREG r0, 0x3D56783A;
78 CHECKREG r1, 0x4E67894B;
79 CHECKREG r2, 0x5F789A5C;
80 CHECKREG r3, 0x6089AB6D;
81 CHECKREG r4, 0x4E67894B;
82 CHECKREG r5, 0x5F789A5C;
83 CHECKREG r6, 0x6089AB6D;
84 CHECKREG r7, 0x719ABC7E;
96 loadsym i0, DATA_ADDR_3, 0x20;
97 loadsym i1, DATA_ADDR_4, 0x20;
98 loadsym i2, DATA_ADDR_5, 0x20;
99 loadsym i3, DATA_ADDR_6, 0x20;
109 loadsym i0, DATA_ADDR_3, 0x20;
110 loadsym i1, DATA_ADDR_4, 0x20;
111 loadsym i2, DATA_ADDR_5, 0x20;
112 loadsym i3, DATA_ADDR_6, 0x20;
121 CHECKREG r0, 0xA0B2C3D4;
122 CHECKREG r1, 0x1B245618;
123 CHECKREG r2, 0x22B36729;
124 CHECKREG r3, 0xBD3C483A;
125 CHECKREG r4, 0xDE64D54B;
126 CHECKREG r5, 0x5F785E6C;
127 CHECKREG r6, 0x30896BF7;
128 CHECKREG r7, 0x719AB770;
132 // Pre-load memory with known data
133 // More data is defined than will actually be used