sim/testsuite/sim/bfin/c_dspldst_ld_drlo_i.s

   1 //Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp
   2 // Spec Reference: c_dspldst ld_drlo_i
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         INIT_R_REGS 0;
   9
  10         loadsym i0, DATA_ADDR_3;
  11         loadsym i1, DATA_ADDR_4;
  12         loadsym i2, DATA_ADDR_5;
  13         loadsym i3, DATA_ADDR_6;
  14
  15 // Load Lower half of Dregs
  16         R0.L = W [ I0 ];
  17         R1.L = W [ I1 ];
  18         R2.L = W [ I2 ];
  19         R3.L = W [ I3 ];
  20         R4.L = W [ I0 ];
  21         R5.L = W [ I1 ];
  22         R6.L = W [ I2 ];
  23         R7.L = W [ I3 ];
  24         CHECKREG r0, 0x00000203;
  25         CHECKREG r1, 0x00002223;
  26         CHECKREG r2, 0x00004243;
  27         CHECKREG r3, 0x00006263;
  28         CHECKREG r4, 0x00000203;
  29         CHECKREG r5, 0x00002223;
  30         CHECKREG r6, 0x00004243;
  31         CHECKREG r7, 0x00006263;
  32
  33         R1.L = W [ I0 ];
  34         R2.L = W [ I1 ];
  35         R3.L = W [ I2 ];
  36         R4.L = W [ I3 ];
  37         R5.L = W [ I0 ];
  38         R6.L = W [ I1 ];
  39         R7.L = W [ I2 ];
  40         R0.L = W [ I3 ];
  41         CHECKREG r0, 0x00006263;
  42         CHECKREG r1, 0x00000203;
  43         CHECKREG r2, 0x00002223;
  44         CHECKREG r3, 0x00004243;
  45         CHECKREG r4, 0x00006263;
  46         CHECKREG r5, 0x00000203;
  47         CHECKREG r6, 0x00002223;
  48         CHECKREG r7, 0x00004243;
  49
  50         R2.L = W [ I0 ];
  51         R3.L = W [ I1 ];
  52         R4.L = W [ I2 ];
  53         R5.L = W [ I3 ];
  54         R6.L = W [ I0 ];
  55         R7.L = W [ I1 ];
  56         R0.L = W [ I2 ];
  57         R1.L = W [ I3 ];
  58         CHECKREG r0, 0x00004243;
  59         CHECKREG r1, 0x00006263;
  60         CHECKREG r2, 0x00000203;
  61         CHECKREG r3, 0x00002223;
  62         CHECKREG r4, 0x00004243;
  63         CHECKREG r5, 0x00006263;
  64         CHECKREG r6, 0x00000203;
  65         CHECKREG r7, 0x00002223;
  66
  67         R3.L = W [ I0 ];
  68         R4.L = W [ I1 ];
  69         R5.L = W [ I2 ];
  70         R6.L = W [ I3 ];
  71         R7.L = W [ I0 ];
  72         R0.L = W [ I1 ];
  73         R1.L = W [ I2 ];
  74         R2.L = W [ I3 ];
  75         CHECKREG r0, 0x00002223;
  76         CHECKREG r1, 0x00004243;
  77         CHECKREG r2, 0x00006263;
  78         CHECKREG r3, 0x00000203;
  79         CHECKREG r4, 0x00002223;
  80         CHECKREG r5, 0x00004243;
  81         CHECKREG r6, 0x00006263;
  82         CHECKREG r7, 0x00000203;
  83
  84         pass
  85
  86 // Pre-load memory with known data
  87 // More data is defined than will actually be used
  88
  89         .data
  90 DATA_ADDR_3:
  91         .dd 0x00010203
  92         .dd 0x04050607
  93         .dd 0x08090A0B
  94         .dd 0x0C0D0E0F
  95         .dd 0x10111213
  96         .dd 0x14151617
  97         .dd 0x18191A1B
  98         .dd 0x1C1D1E1F
  99
 100 DATA_ADDR_4:
 101         .dd 0x20212223
 102         .dd 0x24252627
 103         .dd 0x28292A2B
 104         .dd 0x2C2D2E2F
 105         .dd 0x30313233
 106         .dd 0x34353637
 107         .dd 0x38393A3B
 108         .dd 0x3C3D3E3F
 109
 110 DATA_ADDR_5:
 111         .dd 0x40414243
 112         .dd 0x44454647
 113         .dd 0x48494A4B
 114         .dd 0x4C4D4E4F
 115         .dd 0x50515253
 116         .dd 0x54555657
 117         .dd 0x58595A5B
 118         .dd 0x5C5D5E5F
 119
 120 DATA_ADDR_6:
 121         .dd 0x60616263
 122         .dd 0x64656667
 123         .dd 0x68696A6B
 124         .dd 0x6C6D6E6F
 125         .dd 0x70717273
 126         .dd 0x74757677
 127         .dd 0x78797A7B
 128         .dd 0x7C7D7E7F
 129
 130 DATA_ADDR_7:
 131         .dd 0x80818283
 132         .dd 0x84858687
 133         .dd 0x88898A8B
 134         .dd 0x8C8D8E8F
 135         .dd 0x90919293
 136         .dd 0x94959697
 137         .dd 0x98999A9B
 138         .dd 0x9C9D9E9F
 139
 140 DATA_ADDR_8:
 141         .dd 0xA0A1A2A3
 142         .dd 0xA4A5A6A7
 143         .dd 0xA8A9AAAB
 144         .dd 0xACADAEAF
 145         .dd 0xB0B1B2B3
 146         .dd 0xB4B5B6B7
 147         .dd 0xB8B9BABB
 148         .dd 0xBCBDBEBF
 149         .dd 0xC0C1C2C3
 150         .dd 0xC4C5C6C7
 151         .dd 0xC8C9CACB
 152         .dd 0xCCCDCECF
 153         .dd 0xD0D1D2D3
 154         .dd 0xD4D5D6D7
 155         .dd 0xD8D9DADB
 156         .dd 0xDCDDDEDF
 157         .dd 0xE0E1E2E3
 158         .dd 0xE4E5E6E7
 159         .dd 0xE8E9EAEB
 160         .dd 0xECEDEEEF
 161         .dd 0xF0F1F2F3
 162         .dd 0xF4F5F6F7
 163         .dd 0xF8F9FAFB
 164         .dd 0xFCFDFEFF