sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s

   1 //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp
   2 // Spec Reference: dsp32shiftimm rot:
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         R0 = 0;
   9         ASTAT = R0;
  10
  11
  12         imm32 r0, 0xa1230001;
  13         imm32 r1, 0x1b345678;
  14         imm32 r2, 0x23c56789;
  15         imm32 r3, 0x34d6789a;
  16         imm32 r4, 0x85a789ab;
  17         imm32 r5, 0x967c9abc;
  18         imm32 r6, 0xa789abcd;
  19         imm32 r7, 0xb8912cde;
  20         R0 = ROT R0 BY 1;
  21         R1 = ROT R1 BY 5;
  22         R2 = ROT R2 BY 9;
  23         R3 = ROT R3 BY 8;
  24         R4 = ROT R4 BY 24;
  25         R5 = ROT R5 BY 31;
  26         R6 = ROT R6 BY 14;
  27         R7 = ROT R7 BY 25;
  28         CHECKREG r0, 0x42460002;
  29         CHECKREG r1, 0x668ACF11;
  30         CHECKREG r2, 0x8ACF1323;
  31         CHECKREG r3, 0xD6789A9A;
  32         CHECKREG r4, 0xAB42D3C4;
  33         CHECKREG r5, 0x659F26AF;
  34         CHECKREG r6, 0x6AF354F1;
  35         CHECKREG r7, 0xBCB8912C;
  36
  37         imm32 r0, 0xa1230001;
  38         imm32 r1, 0x1b345678;
  39         imm32 r2, 0x23c56789;
  40         imm32 r3, 0x34d6789a;
  41         imm32 r4, 0x85a789ab;
  42         imm32 r5, 0x967c9abc;
  43         imm32 r6, 0xa789abcd;
  44         imm32 r7, 0xb8912cde;
  45         R6 = ROT R0 BY -3;
  46         R7 = ROT R1 BY -9;
  47         R0 = ROT R2 BY -8;
  48         R1 = ROT R3 BY -7;
  49         R2 = ROT R4 BY -15;
  50         R3 = ROT R5 BY -24;
  51         R4 = ROT R6 BY -31;
  52         R5 = ROT R7 BY -22;
  53         CHECKREG r0, 0x1223C567;
  54         CHECKREG r1, 0x6A69ACF1;
  55         CHECKREG r2, 0x26AD0B4F;
  56         CHECKREG r3, 0xF9357896;
  57         CHECKREG r4, 0xD0918000;
  58         CHECKREG r5, 0x6CD15DE0;
  59         CHECKREG r6, 0x74246000;
  60         CHECKREG r7, 0x780D9A2B;
  61
  62         pass