sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s

   1 //Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp
   2 // Spec Reference: dsp32shift vmax / vmax
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 imm32 r0, 0x11002001;
  11 imm32 r1, 0x12001001;
  12 imm32 r2, 0x11301302;
  13 imm32 r3, 0x43001003;
  14 imm32 r4, 0x11601604;
  15 imm32 r5, 0x71001705;
  16 imm32 r6, 0x81008006;
  17 imm32 r7, 0x1900b007;
  18 A0 = R3;
  19 R1 = VIT_MAX( R1 , R0 ) (ASL);
  20 R2 = VIT_MAX( R2 , R1 ) (ASL);
  21 R3 = VIT_MAX( R3 , R2 ) (ASL);
  22 R4 = VIT_MAX( R4 , R3 ) (ASL);
  23 R5 = VIT_MAX( R5 , R4 ) (ASL);
  24 R6 = VIT_MAX( R6 , R5 ) (ASL);
  25 R7 = VIT_MAX( R7 , R6 ) (ASL);
  26 R0 = VIT_MAX( R0 , R7 ) (ASL);
  27 CHECKREG r0, 0x20018100;
  28 CHECKREG r1, 0x12002001;
  29 CHECKREG r2, 0x13022001;
  30 CHECKREG r3, 0x43002001;
  31 CHECKREG r4, 0x16044300;
  32 CHECKREG r5, 0x71004300;
  33 CHECKREG r6, 0x81007100;
  34 CHECKREG r7, 0x19008100;
  35
  36 imm32 r0, 0x11002001;
  37 imm32 r1, 0xd2001001;
  38 imm32 r2, 0x14301302;
  39 imm32 r3, 0x43001003;
  40 imm32 r4, 0x11f01604;
  41 imm32 r5, 0xb1001705;
  42 imm32 r6, 0xd1008006;
  43 imm32 r7, 0x39056707;
  44 R1 = VIT_MAX( R1 , R3 ) (ASL);
  45 R2 = VIT_MAX( R2 , R4 ) (ASL);
  46 R3 = VIT_MAX( R3 , R6 ) (ASL);
  47 R4 = VIT_MAX( R4 , R5 ) (ASL);
  48 R5 = VIT_MAX( R5 , R7 ) (ASL);
  49 R6 = VIT_MAX( R6 , R0 ) (ASL);
  50 R7 = VIT_MAX( R7 , R1 ) (ASL);
  51 R0 = VIT_MAX( R0 , R2 ) (ASL);
  52 CHECKREG r0, 0x20011604;
  53 CHECKREG r1, 0x10014300;
  54 CHECKREG r2, 0x14301604;
  55 CHECKREG r3, 0x4300D100;
  56 CHECKREG r4, 0x16041705;
  57 CHECKREG r5, 0x17056707;
  58 CHECKREG r6, 0xD1002001;
  59 CHECKREG r7, 0x67074300;
  60
  61 imm32 r0, 0xa1011001;
  62 imm32 r1, 0x1b002001;
  63 imm32 r2, 0x81c01302;
  64 imm32 r3, 0x910d1403;
  65 imm32 r4, 0x2100e504;
  66 imm32 r5, 0x31007f65;
  67 imm32 r6, 0x41007006;
  68 imm32 r7, 0x15001801;
  69 R1 = VIT_MAX( R1 , R0 ) (ASR);
  70 R2 = VIT_MAX( R2 , R1 ) (ASR);
  71 R3 = VIT_MAX( R3 , R2 ) (ASR);
  72 R4 = VIT_MAX( R4 , R3 ) (ASR);
  73 R5 = VIT_MAX( R5 , R4 ) (ASR);
  74 R6 = VIT_MAX( R6 , R5 ) (ASR);
  75 R7 = VIT_MAX( R7 , R6 ) (ASR);
  76 R0 = VIT_MAX( R0 , R7 ) (ASR);
  77 CHECKREG r0, 0x1001910D;
  78 CHECKREG r1, 0x20011001;
  79 CHECKREG r2, 0x81C02001;
  80 CHECKREG r3, 0x910D81C0;
  81 CHECKREG r4, 0x2100910D;
  82 CHECKREG r5, 0x7F65910D;
  83 CHECKREG r6, 0x7006910D;
  84 CHECKREG r7, 0x1801910D;
  85
  86 imm32 r0, 0xe1011001;
  87 imm32 r1, 0x4b002001;
  88 imm32 r2, 0x8fc01302;
  89 imm32 r3, 0x910d1403;
  90 imm32 r4, 0xb100e504;
  91 imm32 r5, 0x41007f65;
  92 imm32 r6, 0xaf007006;
  93 imm32 r7, 0x16001801;
  94 R0 = VIT_MAX( R4 , R0 ) (ASR);
  95 R1 = VIT_MAX( R5 , R1 ) (ASR);
  96 R2 = VIT_MAX( R6 , R2 ) (ASR);
  97 R3 = VIT_MAX( R7 , R3 ) (ASR);
  98 R4 = VIT_MAX( R0 , R4 ) (ASR);
  99 R5 = VIT_MAX( R1 , R5 ) (ASR);
 100 R6 = VIT_MAX( R2 , R6 ) (ASR);
 101 R7 = VIT_MAX( R3 , R7 ) (ASR);
 102 CHECKREG r0, 0xE5041001;
 103 CHECKREG r1, 0x7F654B00;
 104 CHECKREG r2, 0xAF008FC0;
 105 CHECKREG r3, 0x1801910D;
 106 CHECKREG r4, 0x1001E504;
 107 CHECKREG r5, 0x7F657F65;
 108 CHECKREG r6, 0xAF00AF00;
 109 CHECKREG r7, 0x910D1801;
 110
 111
 112
 113 pass