sim/testsuite/sim/bfin/c_dsp32shift_vmax.s

   1 //Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp
   2 // Spec Reference: dsp32shift vmax
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 imm32 r0, 0x11001001;
  11 imm32 r1, 0x11001001;
  12 imm32 r2, 0x12345678;
  13 imm32 r3, 0x11001003;
  14 imm32 r4, 0x11001004;
  15 imm32 r5, 0x11001005;
  16 imm32 r6, 0x11001006;
  17 imm32 r7, 0x11001007;
  18 A0 = R2;
  19 R0.L = VIT_MAX( R0 ) (ASL);
  20 R1.L = VIT_MAX( R1 ) (ASL);
  21 R2.L = VIT_MAX( R2 ) (ASL);
  22 R3.L = VIT_MAX( R3 ) (ASL);
  23 R4.L = VIT_MAX( R4 ) (ASL);
  24 R5.L = VIT_MAX( R5 ) (ASL);
  25 R6.L = VIT_MAX( R6 ) (ASL);
  26 R7.L = VIT_MAX( R7 ) (ASL);
  27 CHECKREG r0, 0x11001100;
  28 CHECKREG r1, 0x11001100;
  29 CHECKREG r2, 0x12345678;
  30 CHECKREG r3, 0x11001100;
  31 CHECKREG r4, 0x11001100;
  32 CHECKREG r5, 0x11001100;
  33 CHECKREG r6, 0x11001100;
  34 CHECKREG r7, 0x11001100;
  35
  36 imm32 r0, 0xa1001001;
  37 imm32 r1, 0x1b001001;
  38 imm32 r2, 0x11c01002;
  39 imm32 r3, 0x110d1003;
  40 imm32 r4, 0x1100e004;
  41 imm32 r5, 0x11001f05;
  42 imm32 r6, 0x11001006;
  43 imm32 r7, 0x11001001;
  44 R1.L = VIT_MAX( R0 ) (ASL);
  45 R2.L = VIT_MAX( R1 ) (ASL);
  46 R3.L = VIT_MAX( R2 ) (ASL);
  47 R4.L = VIT_MAX( R3 ) (ASL);
  48 R5.L = VIT_MAX( R4 ) (ASL);
  49 R6.L = VIT_MAX( R5 ) (ASL);
  50 R7.L = VIT_MAX( R6 ) (ASL);
  51 R0.L = VIT_MAX( R7 ) (ASL);
  52 CHECKREG r0, 0xA1001B00;
  53 CHECKREG r1, 0x1B001001;
  54 CHECKREG r2, 0x11C01B00;
  55 CHECKREG r3, 0x110D1B00;
  56 CHECKREG r4, 0x11001B00;
  57 CHECKREG r5, 0x11001B00;
  58 CHECKREG r6, 0x11001B00;
  59 CHECKREG r7, 0x11001B00;
  60
  61
  62 imm32 r0, 0x20000000;
  63 imm32 r1, 0x4300c001;
  64 imm32 r2, 0x4040c002;
  65 imm32 r3, 0x40056003;
  66 imm32 r4, 0x4000c704;
  67 imm32 r5, 0x4000c085;
  68 imm32 r6, 0x4000c096;
  69 imm32 r7, 0x4000c000;
  70 R0.L = VIT_MAX( R0 ) (ASR);
  71 R1.L = VIT_MAX( R1 ) (ASR);
  72 R2.L = VIT_MAX( R2 ) (ASR);
  73 R3.L = VIT_MAX( R3 ) (ASR);
  74 R4.L = VIT_MAX( R4 ) (ASR);
  75 R5.L = VIT_MAX( R5 ) (ASR);
  76 R6.L = VIT_MAX( R6 ) (ASR);
  77 R7.L = VIT_MAX( R7 ) (ASR);
  78 CHECKREG r0, 0x20002000;
  79 CHECKREG r1, 0x4300C001;
  80 CHECKREG r2, 0x4040C002;
  81 CHECKREG r3, 0x40056003;
  82 CHECKREG r4, 0x40004000;
  83 CHECKREG r5, 0x40004000;
  84 CHECKREG r6, 0x40004000;
  85 CHECKREG r7, 0x4000C000;
  86
  87 imm32 r0, 0x10000000;
  88 imm32 r1, 0x4200c001;
  89 imm32 r2, 0x4030c002;
  90 imm32 r3, 0x4004c003;
  91 imm32 r4, 0x40005004;
  92 imm32 r5, 0x4000c605;
  93 imm32 r6, 0x4000c076;
  94 imm32 r7, 0x4000c008;
  95 R2.L = VIT_MAX( R0 ) (ASR);
  96 R3.L = VIT_MAX( R1 ) (ASR);
  97 R4.L = VIT_MAX( R2 ) (ASR);
  98 R5.L = VIT_MAX( R3 ) (ASR);
  99 R6.L = VIT_MAX( R4 ) (ASR);
 100 R7.L = VIT_MAX( R5 ) (ASR);
 101 R0.L = VIT_MAX( R6 ) (ASR);
 102 R1.L = VIT_MAX( R7 ) (ASR);
 103 CHECKREG r0, 0x10004030;
 104 CHECKREG r1, 0x42004000;
 105 CHECKREG r2, 0x40301000;
 106 CHECKREG r3, 0x4004C001;
 107 CHECKREG r4, 0x40004030;
 108 CHECKREG r5, 0x4000C001;
 109 CHECKREG r6, 0x40004030;
 110 CHECKREG r7, 0x40004000;
 111
 112
 113 pass