sim/testsuite/sim/bfin/c_dsp32shift_expadj_h.s

   1 //Original:/testcases/core/c_dsp32shift_expadj_h/c_dsp32shift_expadj_h.dsp
   2 // Spec Reference: dsp32shift expadj rh
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0x80000008;
  12 imm32 r1, 0x80010008;
  13 imm32 r2, 0x80020008;
  14 imm32 r3, 0x80030008;
  15 imm32 r4, 0x80040008;
  16 imm32 r5, 0x80050008;
  17 imm32 r6, 0x80060008;
  18 imm32 r7, 0x80070008;
  19 R1.L = EXPADJ( R1.H , R0.L );
  20 R2.L = EXPADJ( R2.H , R0.L );
  21 R3.L = EXPADJ( R3.H , R0.L );
  22 R4.L = EXPADJ( R4.H , R0.L );
  23 R5.L = EXPADJ( R5.H , R0.L );
  24 R6.L = EXPADJ( R6.H , R0.L );
  25 R7.L = EXPADJ( R7.H , R0.L );
  26 R0.L = EXPADJ( R0.H , R0.L );
  27 CHECKREG r0, 0x80000000;
  28 CHECKREG r1, 0x80010000;
  29 CHECKREG r2, 0x80020000;
  30 CHECKREG r3, 0x80030000;
  31 CHECKREG r4, 0x80040000;
  32 CHECKREG r5, 0x80050000;
  33 CHECKREG r6, 0x80060000;
  34 CHECKREG r7, 0x80070000;
  35
  36 imm32 r0, 0x90010009;
  37 imm32 r1, 0x00010009;
  38 imm32 r2, 0x90020009;
  39 imm32 r3, 0x90030009;
  40 imm32 r4, 0x90040009;
  41 imm32 r5, 0x90050009;
  42 imm32 r6, 0x90060009;
  43 imm32 r7, 0x90070009;
  44 R0.L = EXPADJ( R0.H , R1.L );
  45 R2.L = EXPADJ( R2.H , R1.L );
  46 R3.L = EXPADJ( R3.H , R1.L );
  47 R4.L = EXPADJ( R4.H , R1.L );
  48 R5.L = EXPADJ( R5.H , R1.L );
  49 R6.L = EXPADJ( R6.H , R1.L );
  50 R7.L = EXPADJ( R7.H , R1.L );
  51 R1.L = EXPADJ( R1.H , R1.L );
  52 CHECKREG r0, 0x90010000;
  53 CHECKREG r1, 0x00010009;
  54 CHECKREG r2, 0x90020000;
  55 CHECKREG r3, 0x90030000;
  56 CHECKREG r4, 0x90040000;
  57 CHECKREG r5, 0x90050000;
  58 CHECKREG r6, 0x90060000;
  59 CHECKREG r7, 0x90070000;
  60
  61
  62 imm32 r0, 0xa001000a;
  63 imm32 r1, 0xa001000a;
  64 imm32 r2, 0xa002000a;
  65 imm32 r3, 0xa003000a;
  66 imm32 r4, 0xa004000a;
  67 imm32 r5, 0xa005000a;
  68 imm32 r6, 0xa006000a;
  69 imm32 r7, 0xa007000a;
  70 R0.L = EXPADJ( R0.H , R2.L );
  71 R1.L = EXPADJ( R1.H , R2.L );
  72 R3.L = EXPADJ( R3.H , R2.L );
  73 R4.L = EXPADJ( R4.H , R2.L );
  74 R5.L = EXPADJ( R5.H , R2.L );
  75 R6.L = EXPADJ( R6.H , R2.L );
  76 R7.L = EXPADJ( R7.H , R2.L );
  77 R2.L = EXPADJ( R2.H , R2.L );
  78 CHECKREG r0, 0xA0010000;
  79 CHECKREG r1, 0xA0010000;
  80 CHECKREG r2, 0xA0020000;
  81 CHECKREG r3, 0xA0030000;
  82 CHECKREG r4, 0xA0040000;
  83 CHECKREG r5, 0xA0050000;
  84 CHECKREG r6, 0xA0060000;
  85 CHECKREG r7, 0xA0070000;
  86
  87 imm32 r0, 0xc001000c;
  88 imm32 r1, 0xc001000c;
  89 imm32 r2, 0xc002000c;
  90 imm32 r3, 0xc003001c;
  91 imm32 r4, 0xc004000c;
  92 imm32 r5, 0xc005000c;
  93 imm32 r6, 0xc006000c;
  94 imm32 r7, 0xc007000c;
  95 R0.L = EXPADJ( R0.H , R3.L );
  96 R1.L = EXPADJ( R1.H , R3.L );
  97 R2.L = EXPADJ( R2.H , R3.L );
  98 R4.L = EXPADJ( R4.H , R3.L );
  99 R5.L = EXPADJ( R5.H , R3.L );
 100 R6.L = EXPADJ( R6.H , R3.L );
 101 R7.L = EXPADJ( R7.H , R3.L );
 102 R3.L = EXPADJ( R3.H , R3.L );
 103 CHECKREG r0, 0xC0010001;
 104 CHECKREG r1, 0xC0010001;
 105 CHECKREG r2, 0xC0020001;
 106 CHECKREG r3, 0xC0030001;
 107 CHECKREG r4, 0xC0040001;
 108 CHECKREG r5, 0xC0050001;
 109 CHECKREG r6, 0xC0060001;
 110 CHECKREG r7, 0xC0070001;
 111
 112 imm32 r0, 0xb0000008;
 113 imm32 r1, 0xb0010008;
 114 imm32 r2, 0xb0020008;
 115 imm32 r3, 0xb0030008;
 116 imm32 r4, 0xb0040008;
 117 imm32 r5, 0xb0050008;
 118 imm32 r6, 0xb0060008;
 119 imm32 r7, 0xb0070008;
 120 R0.L = EXPADJ( R1.H , R4.L );
 121 R1.L = EXPADJ( R2.H , R4.L );
 122 R2.L = EXPADJ( R3.H , R4.L );
 123 R3.L = EXPADJ( R4.H , R4.L );
 124 R5.L = EXPADJ( R5.H , R4.L );
 125 R6.L = EXPADJ( R6.H , R4.L );
 126 R7.L = EXPADJ( R7.H , R4.L );
 127 R4.L = EXPADJ( R0.H , R4.L );
 128 CHECKREG r0, 0xB0000000;
 129 CHECKREG r1, 0xB0010000;
 130 CHECKREG r2, 0xB0020000;
 131 CHECKREG r3, 0xB0030000;
 132 CHECKREG r4, 0xB0040000;
 133 CHECKREG r5, 0xB0050000;
 134 CHECKREG r6, 0xB0060000;
 135 CHECKREG r7, 0xB0070000;
 136
 137 imm32 r0, 0xc0010009;
 138 imm32 r1, 0xc0010009;
 139 imm32 r2, 0xc0020009;
 140 imm32 r3, 0xc0030009;
 141 imm32 r4, 0xc0040009;
 142 imm32 r5, 0xc0050009;
 143 imm32 r6, 0xc0060009;
 144 imm32 r7, 0xc0070009;
 145 R0.L = EXPADJ( R0.H , R5.L );
 146 R1.L = EXPADJ( R2.H , R5.L );
 147 R2.L = EXPADJ( R3.H , R5.L );
 148 R3.L = EXPADJ( R4.H , R5.L );
 149 R4.L = EXPADJ( R5.H , R5.L );
 150 R6.L = EXPADJ( R6.H , R5.L );
 151 R7.L = EXPADJ( R7.H , R5.L );
 152 R5.L = EXPADJ( R1.H , R5.L );
 153 CHECKREG r0, 0xC0010001;
 154 CHECKREG r1, 0xC0010001;
 155 CHECKREG r2, 0xC0020001;
 156 CHECKREG r3, 0xC0030001;
 157 CHECKREG r4, 0xC0040001;
 158 CHECKREG r5, 0xC0050001;
 159 CHECKREG r6, 0xC0060001;
 160 CHECKREG r7, 0xC0070001;
 161
 162
 163 imm32 r0, 0xe001000a;
 164 imm32 r1, 0xe001000a;
 165 imm32 r2, 0xe002000a;
 166 imm32 r3, 0xe003000a;
 167 imm32 r4, 0xe004000a;
 168 imm32 r5, 0xe005000a;
 169 imm32 r6, 0xe006000a;
 170 imm32 r7, 0xe007000a;
 171 R0.L = EXPADJ( R0.H , R6.L );
 172 R1.L = EXPADJ( R1.H , R6.L );
 173 R2.L = EXPADJ( R3.H , R6.L );
 174 R3.L = EXPADJ( R4.H , R6.L );
 175 R4.L = EXPADJ( R5.H , R6.L );
 176 R5.L = EXPADJ( R6.H , R6.L );
 177 R6.L = EXPADJ( R7.H , R6.L );
 178 R7.L = EXPADJ( R2.H , R6.L );
 179 CHECKREG r0, 0xE0010002;
 180 CHECKREG r1, 0xE0010002;
 181 CHECKREG r2, 0xE0020002;
 182 CHECKREG r3, 0xE0030002;
 183 CHECKREG r4, 0xE0040002;
 184 CHECKREG r5, 0xE0050002;
 185 CHECKREG r6, 0xE0060002;
 186 CHECKREG r7, 0xE0070002;
 187
 188 imm32 r0, 0xd001000c;
 189 imm32 r1, 0xd001000c;
 190 imm32 r2, 0xd002000c;
 191 imm32 r3, 0xd003001c;
 192 imm32 r4, 0xd004000c;
 193 imm32 r5, 0xd005000c;
 194 imm32 r6, 0xd006000c;
 195 imm32 r7, 0xd007000c;
 196 R0.L = EXPADJ( R0.H , R7.L );
 197 R1.L = EXPADJ( R1.H , R7.L );
 198 R2.L = EXPADJ( R2.H , R7.L );
 199 R3.L = EXPADJ( R4.H , R7.L );
 200 R4.L = EXPADJ( R5.H , R7.L );
 201 R5.L = EXPADJ( R6.H , R7.L );
 202 R6.L = EXPADJ( R7.H , R7.L );
 203 R7.L = EXPADJ( R3.H , R7.L );
 204 CHECKREG r0, 0xD0010001;
 205 CHECKREG r1, 0xD0010001;
 206 CHECKREG r2, 0xD0020001;
 207 CHECKREG r3, 0xD0030001;
 208 CHECKREG r4, 0xD0040001;
 209 CHECKREG r5, 0xD0050001;
 210 CHECKREG r6, 0xD0060001;
 211 CHECKREG r7, 0xD0070001;
 212
 213
 214 pass