sim/testsuite/sim/bfin/c_dsp32shift_align8.s

   1 //Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp
   2 // Spec Reference: dsp32shift align8
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0x00000001;
   9 imm32 r1, 0x01000801;
  10 imm32 r2, 0x08200802;
  11 imm32 r3, 0x08030803;
  12 imm32 r4, 0x08004804;
  13 imm32 r5, 0x08000505;
  14 imm32 r6, 0x08000866;
  15 imm32 r7, 0x08000807;
  16 R1 = ALIGN8 ( R1 , R0 );
  17 R2 = ALIGN8 ( R2 , R0 );
  18 R3 = ALIGN8 ( R3 , R0 );
  19 R4 = ALIGN8 ( R4 , R0 );
  20 R5 = ALIGN8 ( R5 , R0 );
  21 R6 = ALIGN8 ( R6 , R0 );
  22 R7 = ALIGN8 ( R7 , R0 );
  23 R0 = ALIGN8 ( R0 , R0 );
  24 CHECKREG r0, 0x01000000;
  25 CHECKREG r1, 0x01000000;
  26 CHECKREG r2, 0x02000000;
  27 CHECKREG r3, 0x03000000;
  28 CHECKREG r4, 0x04000000;
  29 CHECKREG r5, 0x05000000;
  30 CHECKREG r6, 0x66000000;
  31 CHECKREG r7, 0x07000000;
  32
  33 imm32 r0, 0x0900d001;
  34 imm32 r1, 0x09000002;
  35 imm32 r2, 0x09400002;
  36 imm32 r3, 0x09100003;
  37 imm32 r4, 0x09020004;
  38 imm32 r5, 0x09003005;
  39 imm32 r6, 0x09000406;
  40 imm32 r7, 0x09000057;
  41 R0 = ALIGN8 ( R0 , R1 );
  42 R2 = ALIGN8 ( R2 , R1 );
  43 R3 = ALIGN8 ( R3 , R1 );
  44 R4 = ALIGN8 ( R4 , R1 );
  45 R5 = ALIGN8 ( R5 , R1 );
  46 R6 = ALIGN8 ( R6 , R1 );
  47 R7 = ALIGN8 ( R7 , R1 );
  48 R1 = ALIGN8 ( R1 , R1 );
  49 CHECKREG r0, 0x01090000;
  50 CHECKREG r1, 0x02090000;
  51 CHECKREG r2, 0x02090000;
  52 CHECKREG r3, 0x03090000;
  53 CHECKREG r4, 0x04090000;
  54 CHECKREG r5, 0x05090000;
  55 CHECKREG r6, 0x06090000;
  56 CHECKREG r7, 0x57090000;
  57
  58
  59 imm32 r0, 0x0a00e001;
  60 imm32 r1, 0x0a00e001;
  61 imm32 r2, 0x0a00000f;
  62 imm32 r3, 0x0a400010;
  63 imm32 r4, 0x0a05e004;
  64 imm32 r5, 0x0a006005;
  65 imm32 r6, 0x0a00e706;
  66 imm32 r7, 0x0a00e087;
  67 R0 = ALIGN8 ( R0 , R2 );
  68 R1 = ALIGN8 ( R1 , R2 );
  69 R3 = ALIGN8 ( R3 , R2 );
  70 R4 = ALIGN8 ( R4 , R2 );
  71 R5 = ALIGN8 ( R5 , R2 );
  72 R6 = ALIGN8 ( R6 , R2 );
  73 R7 = ALIGN8 ( R7 , R2 );
  74 R2 = ALIGN8 ( R2 , R2 );
  75 CHECKREG r0, 0x010A0000;
  76 CHECKREG r1, 0x010A0000;
  77 CHECKREG r2, 0x0F0A0000;
  78 CHECKREG r3, 0x100A0000;
  79 CHECKREG r4, 0x040A0000;
  80 CHECKREG r5, 0x050A0000;
  81 CHECKREG r6, 0x060A0000;
  82 CHECKREG r7, 0x870A0000;
  83
  84 imm32 r0, 0x2b00f001;
  85 imm32 r1, 0x0300f001;
  86 imm32 r2, 0x0b40f002;
  87 imm32 r3, 0x0b050010;
  88 imm32 r4, 0x0b006004;
  89 imm32 r5, 0x0b00f705;
  90 imm32 r6, 0x0b00f086;
  91 imm32 r7, 0x0b00f009;
  92 R0 = ALIGN8 ( R0 , R3 );
  93 R1 = ALIGN8 ( R1 , R3 );
  94 R2 = ALIGN8 ( R2 , R3 );
  95 R4 = ALIGN8 ( R4 , R3 );
  96 R5 = ALIGN8 ( R5 , R3 );
  97 R6 = ALIGN8 ( R6 , R3 );
  98 R7 = ALIGN8 ( R7 , R3 );
  99 R3 = ALIGN8 ( R3 , R3 );
 100 CHECKREG r0, 0x010B0500;
 101 CHECKREG r1, 0x010B0500;
 102 CHECKREG r2, 0x020B0500;
 103 CHECKREG r3, 0x100B0500;
 104 CHECKREG r4, 0x040B0500;
 105 CHECKREG r5, 0x050B0500;
 106 CHECKREG r6, 0x860B0500;
 107 CHECKREG r7, 0x090B0500;
 108
 109 imm32 r0, 0x4c0000c0;
 110 imm32 r1, 0x050100c0;
 111 imm32 r2, 0x0c6200c0;
 112 imm32 r3, 0x0c0700c0;
 113 imm32 r4, 0x0c04800c;
 114 imm32 r5, 0x0c0509c0;
 115 imm32 r6, 0x0c060000;
 116 imm32 r7, 0x0c0700ca;
 117 R0 = ALIGN8 ( R0 , R4 );
 118 R1 = ALIGN8 ( R1 , R4 );
 119 R2 = ALIGN8 ( R2 , R4 );
 120 R3 = ALIGN8 ( R3 , R4 );
 121 R5 = ALIGN8 ( R5 , R4 );
 122 R6 = ALIGN8 ( R6 , R4 );
 123 R7 = ALIGN8 ( R7 , R4 );
 124 R4 = ALIGN8 ( R4 , R4 );
 125 CHECKREG r0, 0xC00C0480;
 126 CHECKREG r1, 0xC00C0480;
 127 CHECKREG r2, 0xC00C0480;
 128 CHECKREG r3, 0xC00C0480;
 129 CHECKREG r4, 0x0C0C0480;
 130 CHECKREG r5, 0xC00C0480;
 131 CHECKREG r6, 0x000C0480;
 132 CHECKREG r7, 0xCA0C0480;
 133
 134 imm32 r0, 0xa00100d0;
 135 imm32 r1, 0xa00100d1;
 136 imm32 r2, 0xa00200d0;
 137 imm32 r3, 0xa00300d0;
 138 imm32 r4, 0xa00400d0;
 139 imm32 r5, 0xa0050007;
 140 imm32 r6, 0xa00600d0;
 141 imm32 r7, 0xa00700d0;
 142 R0 = ALIGN8 ( R0 , R5 );
 143 R1 = ALIGN8 ( R1 , R5 );
 144 R2 = ALIGN8 ( R2 , R5 );
 145 R3 = ALIGN8 ( R3 , R5 );
 146 R4 = ALIGN8 ( R4 , R5 );
 147 R6 = ALIGN8 ( R6 , R5 );
 148 R7 = ALIGN8 ( R7 , R5 );
 149 R5 = ALIGN8 ( R5 , R5 );
 150 CHECKREG r0, 0xD0A00500;
 151 CHECKREG r1, 0xD1A00500;
 152 CHECKREG r2, 0xD0A00500;
 153 CHECKREG r3, 0xD0A00500;
 154 CHECKREG r4, 0xD0A00500;
 155 CHECKREG r5, 0x07A00500;
 156 CHECKREG r6, 0xD0A00500;
 157 CHECKREG r7, 0xD0A00500;
 158
 159 imm32 r0, 0xb2010000;
 160 imm32 r1, 0xb0310000;
 161 imm32 r2, 0xb042000f;
 162 imm32 r3, 0xbf030000;
 163 imm32 r4, 0xba040000;
 164 imm32 r5, 0xbb050000;
 165 imm32 r6, 0xbc060009;
 166 imm32 r7, 0xb0e70000;
 167 R0 = ALIGN8 ( R0 , R6 );
 168 R1 = ALIGN8 ( R1 , R6 );
 169 R2 = ALIGN8 ( R2 , R6 );
 170 R3 = ALIGN8 ( R3 , R6 );
 171 R4 = ALIGN8 ( R4 , R6 );
 172 R5 = ALIGN8 ( R5 , R6 );
 173 R6 = ALIGN8 ( R6 , R6 );
 174 R7 = ALIGN8 ( R7 , R6 );
 175 CHECKREG r0, 0x00BC0600;
 176 CHECKREG r1, 0x00BC0600;
 177 CHECKREG r2, 0x0FBC0600;
 178 CHECKREG r3, 0x00BC0600;
 179 CHECKREG r4, 0x00BC0600;
 180 CHECKREG r5, 0x00BC0600;
 181 CHECKREG r6, 0x09BC0600;
 182 CHECKREG r7, 0x0009BC06;
 183
 184 imm32 r0, 0xd23100e0;
 185 imm32 r1, 0xd04500e0;
 186 imm32 r2, 0xde32f0e0;
 187 imm32 r3, 0xd90300e0;
 188 imm32 r4, 0xd07400e0;
 189 imm32 r5, 0xdef500e0;
 190 imm32 r6, 0xd06600e0;
 191 imm32 r7, 0xd0080023;
 192 R1 = ALIGN8 ( R0 , R7 );
 193 R2 = ALIGN8 ( R1 , R7 );
 194 R3 = ALIGN8 ( R2 , R7 );
 195 R4 = ALIGN8 ( R3 , R7 );
 196 R5 = ALIGN8 ( R4 , R7 );
 197 R6 = ALIGN8 ( R5 , R7 );
 198 R7 = ALIGN8 ( R6 , R7 );
 199 R0 = ALIGN8 ( R7 , R7 );
 200 CHECKREG r0, 0x0000D008;
 201 CHECKREG r1, 0xE0D00800;
 202 CHECKREG r2, 0x00D00800;
 203 CHECKREG r3, 0x00D00800;
 204 CHECKREG r4, 0x00D00800;
 205 CHECKREG r5, 0x00D00800;
 206 CHECKREG r6, 0x00D00800;
 207 CHECKREG r7, 0x00D00800;
 208
 209
 210 pass