sim/testsuite/sim/bfin/c_dsp32mult_pair_u.s

   1 //Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp
   2 // Spec Reference: dsp32mult pair u
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0x8b235625;
   9 imm32 r1, 0x93ba5127;
  10 imm32 r2, 0xa3446725;
  11 imm32 r3, 0x00050027;
  12 imm32 r4, 0xb0ab6d29;
  13 imm32 r5, 0x10ace72b;
  14 imm32 r6, 0xc00c008d;
  15 imm32 r7, 0xd2467029;
  16 R1 = R0.L * R0.L, R0 = R0.L * R0.L (FU);
  17 R3 = R0.L * R1.L, R2 = R0.L * R1.H (FU);
  18 R5 = R1.L * R0.L, R4 = R1.H * R0.L (FU);
  19 R7 = R1.L * R1.L, R6 = R1.H * R1.H (FU);
  20 CHECKREG r0, 0x1CFCE159;
  21 CHECKREG r1, 0x1CFCE159;
  22 CHECKREG r2, 0x19838F9C;
  23 CHECKREG r3, 0xC65D90F1;
  24 CHECKREG r4, 0x19838F9C;
  25 CHECKREG r5, 0xC65D90F1;
  26 CHECKREG r6, 0x03481810;
  27 CHECKREG r7, 0xC65D90F1;
  28
  29 imm32 r0, 0x5b33a635;
  30 imm32 r1, 0x6fbe5137;
  31 imm32 r2, 0x1324b735;
  32 imm32 r3, 0x9006d037;
  33 imm32 r4, 0x80abcb39;
  34 imm32 r5, 0xb0acef3b;
  35 imm32 r6, 0xa00c00dd;
  36 imm32 r7, 0x12469003;
  37 R1 = R2.L * R2.L, R0 = R2.L * R2.L (FU);
  38 R3 = R2.L * R3.L, R2 = R2.L * R3.H (FU);
  39 R5 = R3.L * R2.L, R4 = R3.H * R2.L (FU);
  40 R7 = R3.L * R3.L, R6 = R3.H * R3.H (FU);
  41 CHECKREG r0, 0x831CD0F9;
  42 CHECKREG r1, 0x831CD0F9;
  43 CHECKREG r2, 0x67121B3E;
  44 CHECKREG r3, 0x95026C63;
  45 CHECKREG r4, 0x0FDB4C7C;
  46 CHECKREG r5, 0x0B88B0FA;
  47 CHECKREG r6, 0x56BB5404;
  48 CHECKREG r7, 0x2DE3AE49;
  49
  50 imm32 r0, 0x1b235655;
  51 imm32 r1, 0xc4ba5157;
  52 imm32 r2, 0x63246755;
  53 imm32 r3, 0x00060055;
  54 imm32 r4, 0x90abc509;
  55 imm32 r5, 0x10acef5b;
  56 imm32 r6, 0xb00c005d;
  57 imm32 r7, 0x1246705f;
  58 R1 = R4.L * R4.L, R0 = R4.L * R4.L (FU);
  59 R3 = R4.L * R5.L, R2 = R4.L * R5.H (FU);
  60 R5 = R5.L * R4.L, R4 = R5.H * R4.L (FU);
  61 R7 = R5.L * R5.L, R6 = R5.H * R5.H (FU);
  62 CHECKREG r0, 0x97A6DA51;
  63 CHECKREG r1, 0x97A6DA51;
  64 CHECKREG r2, 0x0CD4F20C;
  65 CHECKREG r3, 0xB8397133;
  66 CHECKREG r4, 0x0CD4F20C;
  67 CHECKREG r5, 0xB8397133;
  68 CHECKREG r6, 0x8491FCB1;
  69 CHECKREG r7, 0x320E1029;
  70
  71 imm32 r0, 0xab235666;
  72 imm32 r1, 0xeaba5166;
  73 imm32 r2, 0x13d48766;
  74 imm32 r3, 0xf00b0066;
  75 imm32 r4, 0x90ab9d69;
  76 imm32 r5, 0x10ac5f6b;
  77 imm32 r6, 0x800cb66d;
  78 imm32 r7, 0x1246707f;
  79 R1 = R6.L * R6.L, R0 = R6.L * R6.L (FU);
  80 R3 = R6.L * R7.L, R2 = R6.L * R7.H (FU);
  81 R5 = R7.L * R6.L, R4 = R7.H * R6.L (FU);
  82 R7 = R7.L * R7.L, R6 = R7.H * R7.H (FU);
  83 CHECKREG r0, 0x81FF2A69;
  84 CHECKREG r1, 0x81FF2A69;
  85 CHECKREG r2, 0x0D058BCE;
  86 CHECKREG r3, 0x502A3013;
  87 CHECKREG r4, 0x0D058BCE;
  88 CHECKREG r5, 0x502A3013;
  89 CHECKREG r6, 0x014DEB24;
  90 CHECKREG r7, 0x316F5F01;
  91
  92 // mix order
  93 imm32 r0, 0xab23a675;
  94 imm32 r1, 0xcfba5127;
  95 imm32 r2, 0x13246705;
  96 imm32 r3, 0x00060007;
  97 imm32 r4, 0x90abcd09;
  98 imm32 r5, 0x10acdfdb;
  99 imm32 r6, 0x000c000d;
 100 imm32 r7, 0x1246f00f;
 101 R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (FU);
 102 R3 = R1.L * R0.H, R2 = R1.H * R0.L (FU);
 103 R5 = R7.H * R4.L, R4 = R7.H * R4.L (FU);
 104 R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (FU);
 105 CHECKREG r0, 0x000085FC;
 106 CHECKREG r1, 0x0002D123;
 107 CHECKREG r2, 0x00010BF8;
 108 CHECKREG r3, 0x00000000;
 109 CHECKREG r4, 0x0EA2B276;
 110 CHECKREG r5, 0x0EA2B276;
 111 CHECKREG r6, 0x0000BE3A;
 112 CHECKREG r7, 0xFFFC0FFE;
 113
 114 imm32 r0, 0x9b235a75;
 115 imm32 r1, 0xc9ba5127;
 116 imm32 r2, 0x13946905;
 117 imm32 r3, 0x00090007;
 118 imm32 r4, 0x90ab9d09;
 119 imm32 r5, 0x10ace9db;
 120 imm32 r6, 0x000c0d9d;
 121 imm32 r7, 0x12467009;
 122 R3 = R6.L * R5.L, R2 = R6.L * R5.H (FU);
 123 R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (FU);
 124 R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (FU);
 125 R7 = R2.H * R7.L, R6 = R2.H * R7.L (FU);
 126 CHECKREG r0, 0x0464B4BB;
 127 CHECKREG r1, 0xB8ADBDCD;
 128 CHECKREG r2, 0x00E2F57C;
 129 CHECKREG r3, 0x0C6F8A4F;
 130 CHECKREG r4, 0x71489715;
 131 CHECKREG r5, 0xD7646535;
 132 CHECKREG r6, 0x0062E7F2;
 133 CHECKREG r7, 0x0062E7F2;
 134
 135 imm32 r0, 0x8b235675;
 136 imm32 r1, 0xc8ba5127;
 137 imm32 r2, 0x13846705;
 138 imm32 r3, 0x00080007;
 139 imm32 r4, 0x90ab8d09;
 140 imm32 r5, 0x10ace8db;
 141 imm32 r6, 0x000c008d;
 142 imm32 r7, 0x12467008;
 143 R3 = R6.H * R5.L, R2 = R6.L * R5.H (FU);
 144 R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (FU);
 145 R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (FU);
 146 R1 = R2.H * R7.L, R0 = R2.L * R7.H (FU);
 147 CHECKREG r0, 0x04A2FAE8;
 148 CHECKREG r1, 0x00043554;
 149 CHECKREG r2, 0x00092EBC;
 150 CHECKREG r3, 0x000AEA44;
 151 CHECKREG r4, 0xB7AF5568;
 152 CHECKREG r5, 0x4A43345C;
 153 CHECKREG r6, 0x00030A1D;
 154 CHECKREG r7, 0x196677B4;
 155
 156 imm32 r0, 0xeb235675;
 157 imm32 r1, 0xceba5127;
 158 imm32 r2, 0x13e46705;
 159 imm32 r3, 0x000e0007;
 160 imm32 r4, 0x90abed09;
 161 imm32 r5, 0x10aceedb;
 162 imm32 r6, 0x000c00ed;
 163 imm32 r7, 0x1246700e;
 164 R1 = R1.H * R4.L, R0 = R1.H * R4.L (FU);
 165 R3 = R2.L * R5.L, R2 = R2.L * R5.H (FU);
 166 R5 = R3.H * R6.L, R4 = R3.L * R6.L (FU);
 167 R7 = R4.L * R0.H, R6 = R4.H * R0.L (FU);
 168 CHECKREG r0, 0xBF69768A;
 169 CHECKREG r1, 0xBF69768A;
 170 CHECKREG r2, 0x06B5875C;
 171 CHECKREG r3, 0x601EC747;
 172 CHECKREG r4, 0x00B87CBB;
 173 CHECKREG r5, 0x0058FBC6;
 174 CHECKREG r6, 0x00553330;
 175 CHECKREG r7, 0x5D42ADB3;
 176
 177
 178
 179 pass