sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s

   1 //Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp
   2 // Spec Reference: dsp32mult single dr tu
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0x8b235625;
   9 imm32 r1, 0x98ba5127;
  10 imm32 r2, 0xa3846725;
  11 imm32 r3, 0x00080027;
  12 imm32 r4, 0xb0ab8d29;
  13 imm32 r5, 0x10ace82b;
  14 imm32 r6, 0xc00c008d;
  15 imm32 r7, 0xd2467028;
  16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU);
  17 R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU);
  18 R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU);
  19 R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU);
  20 R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU);
  21 R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU);
  22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU);
  23 R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU);
  24 CHECKREG r0, 0x1CFC1CFC;
  25 CHECKREG r1, 0x0930114A;
  26 CHECKREG r2, 0x01F5010A;
  27 CHECKREG r3, 0x012A0054;
  28 CHECKREG r4, 0x1CFC1CFC;
  29 CHECKREG r5, 0x1B4E3364;
  30 CHECKREG r6, 0x1B4E3364;
  31 CHECKREG r7, 0x19B95B1D;
  32
  33 imm32 r0, 0x9923a635;
  34 imm32 r1, 0x6f995137;
  35 imm32 r2, 0x1324b735;
  36 imm32 r3, 0x99060037;
  37 imm32 r4, 0x809bcd39;
  38 imm32 r5, 0xb0a99f3b;
  39 imm32 r6, 0xa00c093d;
  40 imm32 r7, 0x12467093;
  41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU);
  42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU);
  43 R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU);
  44 R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU);
  45 R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU);
  46 R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU);
  47 R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU);
  48 R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU);
  49 CHECKREG r0, 0x00700070;
  50 CHECKREG r1, 0x00420042;
  51 CHECKREG r2, 0x0DB20DB2;
  52 CHECKREG r3, 0x082F082F;
  53 CHECKREG r4, 0x0DB20DB2;
  54 CHECKREG r5, 0x6D820B70;
  55 CHECKREG r6, 0x00270004;
  56 CHECKREG r7, 0x00200020;
  57
  58 imm32 r0, 0x19235655;
  59 imm32 r1, 0xc9ba5157;
  60 imm32 r2, 0x63246755;
  61 imm32 r3, 0x0a060055;
  62 imm32 r4, 0x90abc509;
  63 imm32 r5, 0x10acef5b;
  64 imm32 r6, 0xb00a005d;
  65 imm32 r7, 0x1246a05f;
  66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU);
  67 R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU);
  68 R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU);
  69 R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU);
  70 R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU);
  71 R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU);
  72 R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU);
  73 R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU);
  74 CHECKREG r0, 0x6F5897A6;
  75 CHECKREG r1, 0x87430CD4;
  76 CHECKREG r2, 0x0CD40CD4;
  77 CHECKREG r3, 0xDFCB0115;
  78 CHECKREG r4, 0x6F5897A6;
  79 CHECKREG r5, 0x681A8DC9;
  80 CHECKREG r6, 0x53FD3DAA;
  81 CHECKREG r7, 0x39A82A55;
  82
  83 imm32 r0, 0xbb235666;
  84 imm32 r1, 0xefba5166;
  85 imm32 r2, 0x13248766;
  86 imm32 r3, 0xe0060066;
  87 imm32 r4, 0x9eab9d69;
  88 imm32 r5, 0x10ecef6b;
  89 imm32 r6, 0x800ee06d;
  90 imm32 r7, 0x12467e6f;
  91 // test the unsigned U=1
  92 R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU);
  93 R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU);
  94 R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU);
  95 R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU);
  96 R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU);
  97 R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU);
  98 R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU);
  99 R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU);
 100 CHECKREG r0, 0x400EC4BE;
 101 CHECKREG r1, 0x09231005;
 102 CHECKREG r2, 0x09231005;
 103 CHECKREG r3, 0x014D014D;
 104 CHECKREG r4, 0x01240383;
 105 CHECKREG r5, 0x00140014;
 106 CHECKREG r6, 0x400EC4BE;
 107 CHECKREG r7, 0x04920E0B;
 108
 109 // mix order
 110 imm32 r0, 0xac23a675;
 111 imm32 r1, 0xcfba5127;
 112 imm32 r2, 0x13c46705;
 113 imm32 r3, 0x00060007;
 114 imm32 r4, 0x90accd09;
 115 imm32 r5, 0x10acdfdb;
 116 imm32 r6, 0x000cc00d;
 117 imm32 r7, 0x1246fc0f;
 118 R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU);
 119 R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU);
 120 R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU);
 121 R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU);
 122 R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU);
 123 R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU);
 124 R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU);
 125 R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU);
 126 CHECKREG r0, 0x00050005;
 127 CHECKREG r1, 0x02EB02EB;
 128 CHECKREG r2, 0xA3E40C49;
 129 CHECKREG r3, 0x00000000;
 130 CHECKREG r4, 0x00000000;
 131 CHECKREG r5, 0x3CE10003;
 132 CHECKREG r6, 0x00010001;
 133 CHECKREG r7, 0x00050005;
 134
 135 imm32 r0, 0xab235a75;
 136 imm32 r1, 0xcfba5127;
 137 imm32 r2, 0xdd246905;
 138 imm32 r3, 0x00d6d007;
 139 imm32 r4, 0x90abcd09;
 140 imm32 r5, 0x10aceddb;
 141 imm32 r6, 0x000c0d0d;
 142 imm32 r7, 0x1246700f;
 143 R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU);
 144 R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU);
 145 R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU);
 146 R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU);
 147 R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU);
 148 R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU);
 149 R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU);
 150 R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU);
 151 CHECKREG r0, 0x0C370674;
 152 CHECKREG r1, 0x00090423;
 153 CHECKREG r2, 0x0E6606D6;
 154 CHECKREG r3, 0x0078758E;
 155 CHECKREG r4, 0x00430060;
 156 CHECKREG r5, 0x00F00D60;
 157 CHECKREG r6, 0x00000000;
 158 CHECKREG r7, 0x007500DF;
 159
 160 imm32 r0, 0xfb235675;
 161 imm32 r1, 0xcfba5127;
 162 imm32 r2, 0x13f46705;
 163 imm32 r3, 0x000f0007;
 164 imm32 r4, 0x90abfd09;
 165 imm32 r5, 0x10acefdb;
 166 imm32 r6, 0x000c00fd;
 167 imm32 r7, 0x1246700f;
 168 R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU);
 169 R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU);
 170 R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU);
 171 R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU);
 172 R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU);
 173 R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU);
 174 R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU);
 175 R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU);
 176 CHECKREG r0, 0x1B68CBC7;
 177 CHECKREG r1, 0x001D0000;
 178 CHECKREG r2, 0x00550004;
 179 CHECKREG r3, 0x00060025;
 180 CHECKREG r4, 0x00030030;
 181 CHECKREG r5, 0x00050002;
 182 CHECKREG r6, 0x00000000;
 183 CHECKREG r7, 0x00000000;
 184
 185 imm32 r0, 0xab2d5675;
 186 imm32 r1, 0xcfbad127;
 187 imm32 r2, 0x13246d05;
 188 imm32 r3, 0x000600d7;
 189 imm32 r4, 0x908bcd09;
 190 imm32 r5, 0x10a9efdb;
 191 imm32 r6, 0x000c500d;
 192 imm32 r7, 0x1246760f;
 193 R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU);
 194 R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU);
 195 R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU);
 196 R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU);
 197 R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU);
 198 R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU);
 199 R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU);
 200 R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU);
 201 CHECKREG r0, 0x08442F1A;
 202 CHECKREG r1, 0x03102C21;
 203 CHECKREG r2, 0x00000000;
 204 CHECKREG r3, 0x00270027;
 205 CHECKREG r4, 0x662411EE;
 206 CHECKREG r5, 0x00000000;
 207 CHECKREG r6, 0x00000000;
 208 CHECKREG r7, 0x119B119B;
 209
 210
 211
 212 pass