sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s

   1 //Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp
   2 // Spec Reference: dsp32mult single dr munop t
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0xfb235625;
   9 imm32 r1, 0x9fba5127;
  10 imm32 r2, 0xa3ff6725;
  11 imm32 r3, 0x0006f027;
  12 imm32 r4, 0xb0abcd29;
  13 imm32 r5, 0x1facef2b;
  14 imm32 r6, 0xc0fc002d;
  15 imm32 r7, 0xd24f702f;
  16 R4.L = R0.H * R0.L (T);
  17 R5.H = R0.L * R1.L (T);
  18 R6.L = R1.L * R0.H (T);
  19 R7.L = R1.L * R1.L (T);
  20 R0.H = R0.L * R0.L (T);
  21 R1.L = R0.L * R1.L (T);
  22 R2.L = R1.H * R0.L (T);
  23 R3.H = R1.L * R1.L (T);
  24 CHECKREG r0, 0x39F95625;
  25 CHECKREG r1, 0x9FBA369D;
  26 CHECKREG r2, 0xA3FFBF35;
  27 CHECKREG r3, 0x174DF027;
  28 CHECKREG r4, 0xB0ABFCBA;
  29 CHECKREG r5, 0x369DEF2B;
  30 CHECKREG r6, 0xC0FCFCEA;
  31 CHECKREG r7, 0xD24F3373;
  32
  33 imm32 r0, 0xeb23a635;
  34 imm32 r1, 0x6fba5137;
  35 imm32 r2, 0x1324b7e5;
  36 imm32 r3, 0x9e060037;
  37 imm32 r4, 0x80ebcd39;
  38 imm32 r5, 0xb0aeef3b;
  39 imm32 r6, 0xa00ce03d;
  40 imm32 r7, 0x12467e03;
  41 R4.H = R2.L * R2.L (T);
  42 R5.L = R2.L * R3.H (T);
  43 R6.L = R3.H * R2.L (T);
  44 R7.H = R3.L * R3.L (T);
  45 R2.H = R2.L * R2.H (T);
  46 R3.L = R2.H * R3.H (T);
  47 R0.H = R3.L * R2.L (T);
  48 R1.L = R3.L * R3.L (T);
  49 CHECKREG r0, 0xFB59A635;
  50 CHECKREG r1, 0x6FBA0088;
  51 CHECKREG r2, 0xF537B7E5;
  52 CHECKREG r3, 0x9E060841;
  53 CHECKREG r4, 0x289ECD39;
  54 CHECKREG r5, 0xB0AE3731;
  55 CHECKREG r6, 0xA00C3731;
  56 CHECKREG r7, 0x00007E03;
  57
  58 imm32 r0, 0xdd235655;
  59 imm32 r1, 0xc4dd5157;
  60 imm32 r2, 0x6324d755;
  61 imm32 r3, 0x00060055;
  62 imm32 r4, 0x90dbc509;
  63 imm32 r5, 0x10adef5b;
  64 imm32 r6, 0xb00cd05d;
  65 imm32 r7, 0x12467d5f;
  66 R0.L = R4.L * R4.H (T);
  67 R1.H = R4.H * R5.L (T);
  68 R2.L = R5.H * R4.L (T);
  69 R3.L = R5.L * R5.L (T);
  70 R4.H = R4.L * R4.H (T);
  71 R5.L = R4.L * R5.H (T);
  72 R6.H = R5.H * R4.H (T);
  73 R7.L = R5.H * R5.H (T);
  74 CHECKREG r0, 0xDD233333;
  75 CHECKREG r1, 0x0E735157;
  76 CHECKREG r2, 0x6324F851;
  77 CHECKREG r3, 0x0006022A;
  78 CHECKREG r4, 0x3333C509;
  79 CHECKREG r5, 0x10ADF851;
  80 CHECKREG r6, 0x06ABD05D;
  81 CHECKREG r7, 0x1246022C;
  82
  83 imm32 r0, 0xcb235666;
  84 imm32 r1, 0xefba5166;
  85 imm32 r2, 0x1c248766;
  86 imm32 r3, 0xf0060066;
  87 imm32 r4, 0x90cb9d69;
  88 imm32 r5, 0x10acef6b;
  89 imm32 r6, 0x800cc06d;
  90 imm32 r7, 0x12467c6f;
  91 // test the unsigned U=1
  92 R0.L = R6.L * R6.L (T);
  93 R1.H = R6.H * R7.L (T);
  94 R2.L = R7.L * R6.L (T);
  95 R3.L = R7.L * R7.L (T);
  96 R6.L = R6.L * R6.L (T);
  97 R7.L = R6.L * R7.L (T);
  98 R4.L = R7.L * R6.L (T);
  99 R5.L = R7.L * R7.L (T);
 100 CHECKREG r0, 0xCB231F93;
 101 CHECKREG r1, 0x839C5166;
 102 CHECKREG r2, 0x1C24C232;
 103 CHECKREG r3, 0xF00678F7;
 104 CHECKREG r4, 0x90CB0792;
 105 CHECKREG r5, 0x10AC075B;
 106 CHECKREG r6, 0x800C1F93;
 107 CHECKREG r7, 0x12461EB1;
 108
 109 // mix order
 110 imm32 r0, 0xab23a675;
 111 imm32 r1, 0xcfba5127;
 112 imm32 r2, 0x13246705;
 113 imm32 r3, 0xe0060007;
 114 imm32 r4, 0x9eabcd09;
 115 imm32 r5, 0x10ecdfdb;
 116 imm32 r6, 0x000e000d;
 117 imm32 r7, 0x1246e00f;
 118 R0.H = R0.L * R7.H (T);
 119 R1.L = R1.H * R6.H (T);
 120 R2.L = R2.L * R5.L (T);
 121 R3.H = R3.H * R4.H (T);
 122 R4.L = R4.L * R3.H (T);
 123 R5.L = R5.H * R2.H (T);
 124 R6.H = R6.H * R1.L (T);
 125 R7.L = R7.L * R0.H (T);
 126 CHECKREG r0, 0xF337A675;
 127 CHECKREG r1, 0xCFBAFFFA;
 128 CHECKREG r2, 0x1324E620;
 129 CHECKREG r3, 0x18500007;
 130 CHECKREG r4, 0x9EABF651;
 131 CHECKREG r5, 0x10EC0287;
 132 CHECKREG r6, 0xFFFF000D;
 133 CHECKREG r7, 0x12460330;
 134
 135 imm32 r0, 0x9b235a75;
 136 imm32 r1, 0xcfba5127;
 137 imm32 r2, 0x93246905;
 138 imm32 r3, 0x09060007;
 139 imm32 r4, 0x909bcd09;
 140 imm32 r5, 0x10a9e9db;
 141 imm32 r6, 0x000c9d0d;
 142 imm32 r7, 0x1246790f;
 143 R0.L = R7.L * R0.H (T);
 144 R1.L = R6.L * R1.L (T);
 145 R2.H = R5.L * R2.L (T);
 146 R3.L = R4.H * R3.L (T);
 147 R4.L = R3.H * R4.H (T);
 148 R5.H = R2.H * R5.L (T);
 149 R6.L = R1.H * R6.L (T);
 150 R7.L = R0.L * R7.L (T);
 151 CHECKREG r0, 0x9B23A09B;
 152 CHECKREG r1, 0xCFBAC144;
 153 CHECKREG r2, 0xEDD46905;
 154 CHECKREG r3, 0x0906FFF9;
 155 CHECKREG r4, 0x909BF825;
 156 CHECKREG r5, 0x0324E9DB;
 157 CHECKREG r6, 0x000C2551;
 158 CHECKREG r7, 0x1246A5C7;
 159
 160 imm32 r0, 0xa9235675;
 161 imm32 r1, 0xc8ba5127;
 162 imm32 r2, 0x13246705;
 163 imm32 r3, 0x08060007;
 164 imm32 r4, 0x908bcd09;
 165 imm32 r5, 0x10a88fdb;
 166 imm32 r6, 0x000c080d;
 167 imm32 r7, 0x1246708f;
 168 R2.L = R3.L * R6.L (T);
 169 R3.L = R4.H * R7.L (T);
 170 R0.H = R7.L * R0.L, R0.L = R7.H * R0.H (T);
 171 R1.H = R6.L * R1.L (T);
 172 R4.L = R5.H * R2.L (T);
 173 R5.L = R2.L * R3.L (T);
 174 R6.L = R0.L * R4.L (T);
 175 R7.H = R1.H * R5.L (T);
 176 CHECKREG r0, 0x4C06F399;
 177 CHECKREG r1, 0x051A5127;
 178 CHECKREG r2, 0x13240000;
 179 CHECKREG r3, 0x08069DFD;
 180 CHECKREG r4, 0x908B0000;
 181 CHECKREG r5, 0x10A80000;
 182 CHECKREG r6, 0x000C0000;
 183 CHECKREG r7, 0x0000708F;
 184
 185 imm32 r0, 0x7b235675;
 186 imm32 r1, 0xcfba5127;
 187 imm32 r2, 0x17246705;
 188 imm32 r3, 0x00760007;
 189 imm32 r4, 0x907bcd09;
 190 imm32 r5, 0x10a7efdb;
 191 imm32 r6, 0x000c700d;
 192 imm32 r7, 0x1246770f;
 193 R4.L = R5.L * R3.L (T);
 194 R6.L = R6.L * R4.H (T);
 195 R0.H = R7.L * R5.H (T);
 196 R1.L = R0.L * R6.L (T);
 197 R2.L = R1.L * R7.H (T);
 198 R5.L = R2.L * R2.H (T);
 199 R3.H = R3.H * R0.L (T);
 200 R7.L = R4.H * R1.H (T);
 201 CHECKREG r0, 0x0F7D5675;
 202 CHECKREG r1, 0xCFBABE0F;
 203 CHECKREG r2, 0x1724F696;
 204 CHECKREG r3, 0x004F0007;
 205 CHECKREG r4, 0x907BFFFF;
 206 CHECKREG r5, 0x10A7FE4C;
 207 CHECKREG r6, 0x000C9E60;
 208 CHECKREG r7, 0x12462A0E;
 209
 210
 211
 212 pass