sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s

   1 //Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp
   2 // Spec Reference: dsp32mult single dr munop i
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0xfb235625;
   9 imm32 r1, 0x9fba5127;
  10 imm32 r2, 0xa3ff6725;
  11 imm32 r3, 0x0006f027;
  12 imm32 r4, 0xb0abcd29;
  13 imm32 r5, 0x1facef2b;
  14 imm32 r6, 0xc0fc002d;
  15 imm32 r7, 0xd24f702f;
  16 R4.L = R0.H * R0.L (IS);
  17 R5.H = R0.L * R1.L (IS);
  18 R6.L = R1.L * R0.H (IS);
  19 R7.L = R1.L * R1.L (IS);
  20 R0.H = R0.L * R0.L (IS);
  21 R1.L = R0.L * R1.L (IS);
  22 R2.L = R1.H * R0.L (IS);
  23 R3.H = R1.L * R1.L (IS);
  24 CHECKREG r0, 0x7FFF5625;
  25 CHECKREG r1, 0x9FBA7FFF;
  26 CHECKREG r2, 0xA3FF8000;
  27 CHECKREG r3, 0x7FFFF027;
  28 CHECKREG r4, 0xB0AB8000;
  29 CHECKREG r5, 0x7FFFEF2B;
  30 CHECKREG r6, 0xC0FC8000;
  31 CHECKREG r7, 0xD24F7FFF;
  32
  33 imm32 r0, 0xeb23a635;
  34 imm32 r1, 0x6fba5137;
  35 imm32 r2, 0x1324b7e5;
  36 imm32 r3, 0x9e060037;
  37 imm32 r4, 0x80ebcd39;
  38 imm32 r5, 0xb0aeef3b;
  39 imm32 r6, 0xa00ce03d;
  40 imm32 r7, 0x12467e03;
  41 R5.H = R2.L * R2.L (IS);
  42 R6.L = R2.L * R3.H (IS);
  43 R7.L = R3.H * R2.L (IS);
  44 R0.H = R3.L * R3.L (IS);
  45 R1.H = R2.L * R2.H (IS);
  46 R2.L = R2.H * R3.H (IS);
  47 R3.H = R3.L * R2.L (IS);
  48 R4.L = R3.L * R3.L (IS);
  49 CHECKREG r0, 0x0BD1A635;
  50 CHECKREG r1, 0x80005137;
  51 CHECKREG r2, 0x13248000;
  52 CHECKREG r3, 0x80000037;
  53 CHECKREG r4, 0x80EB0BD1;
  54 CHECKREG r5, 0x7FFFEF3B;
  55 CHECKREG r6, 0xA00C7FFF;
  56 CHECKREG r7, 0x12467FFF;
  57
  58 imm32 r0, 0xdd235655;
  59 imm32 r1, 0xc4dd5157;
  60 imm32 r2, 0x6324d755;
  61 imm32 r3, 0x00060055;
  62 imm32 r4, 0x90dbc509;
  63 imm32 r5, 0x10adef5b;
  64 imm32 r6, 0xb00cd05d;
  65 imm32 r7, 0x12467d5f;
  66 R0.L = R4.L * R4.H (IS);
  67 R1.H = R4.H * R5.L (IS);
  68 R2.L = R5.H * R4.L (IS);
  69 R3.L = R5.L * R5.L (IS);
  70 R4.H = R4.L * R4.H (IS);
  71 R5.L = R4.L * R5.H (IS);
  72 R6.H = R5.H * R4.H (IS);
  73 R7.L = R5.H * R5.H (IS);
  74 CHECKREG r0, 0xDD237FFF;
  75 CHECKREG r1, 0x7FFF5157;
  76 CHECKREG r2, 0x63248000;
  77 CHECKREG r3, 0x00067FFF;
  78 CHECKREG r4, 0x7FFFC509;
  79 CHECKREG r5, 0x10AD8000;
  80 CHECKREG r6, 0x7FFFD05D;
  81 CHECKREG r7, 0x12467FFF;
  82
  83 imm32 r0, 0xcb235666;
  84 imm32 r1, 0xefba5166;
  85 imm32 r2, 0x1c248766;
  86 imm32 r3, 0xf0060066;
  87 imm32 r4, 0x90cb9d69;
  88 imm32 r5, 0x10acef6b;
  89 imm32 r6, 0x800cc06d;
  90 imm32 r7, 0x12467c6f;
  91 // test the unsigned U=1
  92 R0.L = R6.L * R6.L (IS);
  93 R1.H = R6.H * R7.L (IS);
  94 R2.L = R7.L * R6.L (IS);
  95 R3.L = R7.L * R7.L (IS);
  96 R6.H = R6.H * R6.H (IS);
  97 R7.L = R6.L * R7.L (IS);
  98 R4.H = R7.H * R6.H (IS);
  99 R5.L = R7.L * R7.L (IS);
 100 CHECKREG r0, 0xCB237FFF;
 101 CHECKREG r1, 0x80005166;
 102 CHECKREG r2, 0x1C248000;
 103 CHECKREG r3, 0xF0067FFF;
 104 CHECKREG r4, 0x7FFF9D69;
 105 CHECKREG r5, 0x10AC7FFF;
 106 CHECKREG r6, 0x7FFFC06D;
 107 CHECKREG r7, 0x12468000;
 108
 109 // mix order
 110 imm32 r0, 0xab23a675;
 111 imm32 r1, 0xcfba5127;
 112 imm32 r2, 0x13246705;
 113 imm32 r3, 0xe0060007;
 114 imm32 r4, 0x9eabcd09;
 115 imm32 r5, 0x10ecdfdb;
 116 imm32 r6, 0x000e000d;
 117 imm32 r7, 0x1246e00f;
 118 R0.H = R0.L * R7.H (IS);
 119 R1.L = R1.H * R6.H (IS);
 120 R2.L = R2.L * R5.L (IS);
 121 R3.H = R3.H * R4.H (IS);
 122 R4.L = R4.L * R3.H (IS);
 123 R5.L = R5.H * R2.H (IS);
 124 R6.H = R6.H * R1.L (IS);
 125 R7.L = R7.L * R0.H (IS);
 126 CHECKREG r0, 0x8000A675;
 127 CHECKREG r1, 0xCFBA8000;
 128 CHECKREG r2, 0x13248000;
 129 CHECKREG r3, 0x7FFF0007;
 130 CHECKREG r4, 0x9EAB8000;
 131 CHECKREG r5, 0x10EC7FFF;
 132 CHECKREG r6, 0x8000000D;
 133 CHECKREG r7, 0x12467FFF;
 134
 135 imm32 r0, 0x9b235a75;
 136 imm32 r1, 0xcfba5127;
 137 imm32 r2, 0x93246905;
 138 imm32 r3, 0x09060007;
 139 imm32 r4, 0x909bcd09;
 140 imm32 r5, 0x10a9e9db;
 141 imm32 r6, 0x000c9d0d;
 142 imm32 r7, 0x1246790f;
 143 R0.L = R7.L * R0.H (IS);
 144 R1.L = R6.L * R1.L (IS);
 145 R2.H = R5.L * R2.L (IS);
 146 R3.L = R4.H * R3.L (IS);
 147 R4.L = R3.H * R4.H (IS);
 148 R5.H = R2.H * R5.L (IS);
 149 R6.L = R1.H * R6.L (IS);
 150 R7.L = R0.L * R7.L (IS);
 151 CHECKREG r0, 0x9B238000;
 152 CHECKREG r1, 0xCFBA8000;
 153 CHECKREG r2, 0x80006905;
 154 CHECKREG r3, 0x09068000;
 155 CHECKREG r4, 0x909B8000;
 156 CHECKREG r5, 0x7FFFE9DB;
 157 CHECKREG r6, 0x000C7FFF;
 158 CHECKREG r7, 0x12468000;
 159
 160 imm32 r0, 0xa9235675;
 161 imm32 r1, 0xc8ba5127;
 162 imm32 r2, 0x13246705;
 163 imm32 r3, 0x08060007;
 164 imm32 r4, 0x908bcd09;
 165 imm32 r5, 0x10a88fdb;
 166 imm32 r6, 0x000c080d;
 167 imm32 r7, 0x1246708f;
 168 R2.L = R0.L * R6.L (IS);
 169 R3.L = R1.H * R7.L (IS);
 170 R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS);
 171 R1.H = R3.L * R1.L (IS);
 172 R4.L = R4.H * R2.L (IS);
 173 R5.L = R5.L * R3.L (IS);
 174 R6.L = R6.L * R4.L (IS);
 175 R7.H = R7.H * R5.L (IS);
 176 CHECKREG r0, 0x7FFF8000;
 177 CHECKREG r1, 0x80005127;
 178 CHECKREG r2, 0x13247FFF;
 179 CHECKREG r3, 0x08068000;
 180 CHECKREG r4, 0x908B8000;
 181 CHECKREG r5, 0x10A87FFF;
 182 CHECKREG r6, 0x000C8000;
 183 CHECKREG r7, 0x7FFF708F;
 184
 185 imm32 r0, 0x7b235675;
 186 imm32 r1, 0xcfba5127;
 187 imm32 r2, 0x17246705;
 188 imm32 r3, 0x00760007;
 189 imm32 r4, 0x907bcd09;
 190 imm32 r5, 0x10a7efdb;
 191 imm32 r6, 0x000c700d;
 192 imm32 r7, 0x1246770f;
 193 R4.L = R5.L * R2.L (IS);
 194 R6.L = R6.L * R3.H (IS);
 195 R0.H = R7.L * R4.H (IS);
 196 R1.L = R0.H * R5.L (IS);
 197 R2.L = R1.L * R6.L (IS);
 198 R5.L = R2.L * R7.H (IS);
 199 R3.H = R3.H * R0.L (IS);
 200 R7.L = R4.H * R1.H (IS);
 201 CHECKREG r0, 0x80005675;
 202 CHECKREG r1, 0xCFBA7FFF;
 203 CHECKREG r2, 0x17247FFF;
 204 CHECKREG r3, 0x7FFF0007;
 205 CHECKREG r4, 0x907B8000;
 206 CHECKREG r5, 0x10A77FFF;
 207 CHECKREG r6, 0x000C7FFF;
 208 CHECKREG r7, 0x12467FFF;
 209
 210
 211
 212 pass