sim/testsuite/sim/bfin/c_dsp32mult_dr.s

   1 //Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp
   2 // Spec Reference: dsp32mult single dr
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0x8b235625;
   9 imm32 r1, 0x93ba5127;
  10 imm32 r2, 0xa3446725;
  11 imm32 r3, 0x00050027;
  12 imm32 r4, 0xb0ab6d29;
  13 imm32 r5, 0x10ace72b;
  14 imm32 r6, 0xc00c008d;
  15 imm32 r7, 0xd2467029;
  16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L;
  17 R5.H = R0.L * R1.L, R5.L = R0.L * R1.H;
  18 R6.H = R1.L * R0.L, R6.L = R1.H * R0.L;
  19 R7.H = R1.L * R1.L, R7.L = R1.H * R1.H;
  20 R0.H = R0.L * R0.L, R0.L = R0.L * R0.L;
  21 R1.H = R0.L * R1.L, R1.L = R0.L * R1.H;
  22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L;
  23 R3.H = R1.L * R1.L, R3.L = R1.H * R1.H;
  24 CHECKREG r0, 0x39FA39FA;
  25 CHECKREG r1, 0x24C2CEF5;
  26 CHECKREG r2, 0xE9C910A6;
  27 CHECKREG r3, 0x12CA0A8E;
  28 CHECKREG r4, 0x39FA39FA;
  29 CHECKREG r5, 0x369EB722;
  30 CHECKREG r6, 0x369EB722;
  31 CHECKREG r7, 0x33735B96;
  32
  33 imm32 r0, 0x5b33a635;
  34 imm32 r1, 0x6fbe5137;
  35 imm32 r2, 0x1324b735;
  36 imm32 r3, 0x9006d037;
  37 imm32 r4, 0x80abcb39;
  38 imm32 r5, 0xb0acef3b;
  39 imm32 r6, 0xa00c00dd;
  40 imm32 r7, 0x12469003;
  41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L;
  42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H;
  43 R6.H = R3.L * R2.H, R6.L = R3.L * R2.L;
  44 R7.H = R3.L * R3.H, R7.L = R3.L * R3.H;
  45 R2.H = R2.L * R2.H, R2.L = R2.H * R2.L;
  46 R3.H = R2.L * R3.H, R3.L = R2.H * R3.H;
  47 R0.H = R3.L * R2.H, R0.L = R3.L * R2.L;
  48 R1.H = R3.L * R3.H, R1.L = R3.L * R3.H;
  49 CHECKREG r0, 0xFF31FF31;
  50 CHECKREG r1, 0x00B500B5;
  51 CHECKREG r2, 0xF51DF51D;
  52 CHECKREG r3, 0x09860986;
  53 CHECKREG r4, 0xF51DF51D;
  54 CHECKREG r5, 0x3FAEEF41;
  55 CHECKREG r6, 0xF8DB1B2D;
  56 CHECKREG r7, 0x29CE29CE;
  57
  58 imm32 r0, 0x1b235655;
  59 imm32 r1, 0xc4ba5157;
  60 imm32 r2, 0x63246755;
  61 imm32 r3, 0x00060055;
  62 imm32 r4, 0x90abc509;
  63 imm32 r5, 0x10acef5b;
  64 imm32 r6, 0xb00c005d;
  65 imm32 r7, 0x1246705f;
  66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L;
  67 R1.H = R4.H * R5.L, R1.L = R4.L * R5.H;
  68 R2.H = R5.H * R4.L, R2.L = R5.H * R4.L;
  69 R3.H = R5.H * R5.L, R3.L = R5.H * R5.H;
  70 R4.H = R4.H * R4.L, R4.L = R4.L * R4.L;
  71 R5.H = R4.H * R5.L, R5.L = R4.L * R5.H;
  72 R6.H = R5.H * R4.L, R6.L = R5.H * R4.L;
  73 R7.H = R5.H * R5.L, R7.L = R5.H * R5.H;
  74 CHECKREG r0, 0x33491B2A;
  75 CHECKREG r1, 0x0E7AF852;
  76 CHECKREG r2, 0xF852F852;
  77 CHECKREG r3, 0xFDD5022C;
  78 CHECKREG r4, 0x33491B2A;
  79 CHECKREG r5, 0xF955038A;
  80 CHECKREG r6, 0xFE96FE96;
  81 CHECKREG r7, 0xFFD10059;
  82
  83 imm32 r0, 0xab235666;
  84 imm32 r1, 0xeaba5166;
  85 imm32 r2, 0x13d48766;
  86 imm32 r3, 0xf00b0066;
  87 imm32 r4, 0x90ab9d69;
  88 imm32 r5, 0x10ac5f6b;
  89 imm32 r6, 0x800cb66d;
  90 imm32 r7, 0x1246707f;
  91 // test the unsigned U=1
  92 R0.H = R6.H * R6.H, R0.L = R6.L * R6.L;
  93 R1.H = R6.H * R7.H, R1.L = R6.L * R7.H;
  94 R2.H = R7.H * R6.H, R2.L = R7.H * R6.L;
  95 R3.H = R7.H * R7.H, R3.L = R7.H * R7.H;
  96 R6.H = R6.H * R6.H, R6.L = R6.L * R6.L;
  97 R7.H = R6.H * R7.H, R7.L = R6.L * R7.H;
  98 R4.H = R7.H * R6.H, R4.L = R7.H * R6.L;
  99 R5.H = R7.H * R7.H, R5.L = R7.H * R7.H;
 100 CHECKREG r0, 0x7FE82A4A;
 101 CHECKREG r1, 0xEDBCF57F;
 102 CHECKREG r2, 0xEDBCF57F;
 103 CHECKREG r3, 0x029C029C;
 104 CHECKREG r4, 0x12400609;
 105 CHECKREG r5, 0x029B029B;
 106 CHECKREG r6, 0x7FE82A4A;
 107 CHECKREG r7, 0x1243060A;
 108
 109 // mix order
 110 imm32 r0, 0xab23a675;
 111 imm32 r1, 0xcfba5127;
 112 imm32 r2, 0x13246705;
 113 imm32 r3, 0x00060007;
 114 imm32 r4, 0x90abcd09;
 115 imm32 r5, 0x10acdfdb;
 116 imm32 r6, 0x000c000d;
 117 imm32 r7, 0x1246f00f;
 118 R0.H = R0.L * R7.H (M), R0.L = R0.H * R7.L;
 119 R1.H = R1.H * R6.H, R1.L = R1.H * R6.H;
 120 R2.H = R2.H * R5.L, R2.L = R2.L * R5.L;
 121 R3.H = R3.H * R4.L (M), R3.L = R3.H * R4.L;
 122 R4.H = R4.L * R3.L, R4.L = R4.L * R3.H;
 123 R5.H = R5.H * R2.L, R5.L = R5.H * R2.L;
 124 R6.H = R6.L * R1.H, R6.L = R6.L * R1.L;
 125 R7.H = R7.H * R0.L, R7.L = R7.H * R0.H;
 126 CHECKREG r0, 0xF99C0A92;
 127 CHECKREG r1, 0xFFFBFFFB;
 128 CHECKREG r2, 0xFB31E621;
 129 CHECKREG r3, 0x0005FFFE;
 130 CHECKREG r4, 0x0001FFFE;
 131 CHECKREG r5, 0xFCA1FCA1;
 132 CHECKREG r6, 0x00000000;
 133 CHECKREG r7, 0x0182FF16;
 134
 135 imm32 r0, 0x9b235a75;
 136 imm32 r1, 0xc9ba5127;
 137 imm32 r2, 0x13946905;
 138 imm32 r3, 0x00090007;
 139 imm32 r4, 0x90ab9d09;
 140 imm32 r5, 0x10ace9db;
 141 imm32 r6, 0x000c0d9d;
 142 imm32 r7, 0x12467009;
 143 R0.H = R7.H * R0.H, R0.L = R7.L * R0.L;
 144 R1.H = R6.H * R1.L (M), R1.L = R6.H * R1.L;
 145 R2.H = R5.H * R2.H, R2.L = R5.L * R2.L;
 146 R3.H = R4.L * R3.H, R3.L = R4.H * R3.L;
 147 R4.H = R3.H * R4.H, R4.L = R3.L * R4.L;
 148 R5.H = R2.H * R5.L (M), R5.L = R2.H * R5.L;
 149 R6.H = R1.L * R6.L, R6.L = R1.L * R6.H;
 150 R7.H = R0.L * R7.H, R7.L = R0.H * R7.H;
 151 CHECKREG r0, 0xF19A4F2D;
 152 CHECKREG r1, 0x00040008;
 153 CHECKREG r2, 0x028DEDD5;
 154 CHECKREG r3, 0xFFF9FFFA;
 155 CHECKREG r4, 0x00060005;
 156 CHECKREG r5, 0x0255FF8F;
 157 CHECKREG r6, 0x00010000;
 158 CHECKREG r7, 0x0B4EFDF2;
 159
 160 imm32 r0, 0x8b235675;
 161 imm32 r1, 0xc8ba5127;
 162 imm32 r2, 0x13846705;
 163 imm32 r3, 0x00080007;
 164 imm32 r4, 0x90ab8d09;
 165 imm32 r5, 0x10ace8db;
 166 imm32 r6, 0x000c008d;
 167 imm32 r7, 0x12467008;
 168 R2.H = R0.L * R6.L, R2.L = R0.L * R6.H;
 169 R3.H = R1.H * R7.H (M), R3.L = R1.L * R7.L;
 170 R0.H = R2.L * R0.L, R0.L = R2.H * R0.H;
 171 R1.H = R3.H * R1.L, R1.L = R3.L * R1.H;
 172 R4.H = R4.L * R2.L, R4.L = R4.L * R2.H;
 173 R5.H = R5.L * R3.H, R5.L = R5.H * R3.L;
 174 R6.H = R6.H * R4.L (M), R6.L = R6.L * R4.H;
 175 R7.H = R7.L * R5.L, R7.L = R7.H * R5.H;
 176 CHECKREG r0, 0x0005FFA9;
 177 CHECKREG r1, 0xFD80E154;
 178 CHECKREG r2, 0x005F0008;
 179 CHECKREG r3, 0xFC0E4707;
 180 CHECKREG r4, 0xFFF9FFAB;
 181 CHECKREG r5, 0x00B70940;
 182 CHECKREG r6, 0x000C0000;
 183 CHECKREG r7, 0x0819001A;
 184
 185 imm32 r0, 0xeb235675;
 186 imm32 r1, 0xceba5127;
 187 imm32 r2, 0x13e46705;
 188 imm32 r3, 0x000e0007;
 189 imm32 r4, 0x90abed09;
 190 imm32 r5, 0x10aceedb;
 191 imm32 r6, 0x000c00ed;
 192 imm32 r7, 0x1246700e;
 193 R4.H = R5.L * R2.L, R4.L = R5.L * R2.H;
 194 R6.H = R6.H * R3.L (M), R6.L = R6.L * R3.H;
 195 R0.H = R7.L * R4.H, R0.L = R7.H * R4.H;
 196 R1.H = R0.L * R5.H, R1.L = R0.L * R5.L;
 197 R2.H = R1.H * R6.L (M), R2.L = R1.L * R6.H;
 198 R5.H = R2.L * R7.H, R5.L = R2.H * R7.L;
 199 R3.H = R3.L * R0.L, R3.L = R3.L * R0.H;
 200 R7.H = R4.L * R1.L, R7.L = R4.L * R1.H;
 201 CHECKREG r0, 0xF3ECFE08;
 202 CHECKREG r1, 0xFFBE0044;
 203 CHECKREG r2, 0x00000000;
 204 CHECKREG r3, 0x0000FFFF;
 205 CHECKREG r4, 0xF234FD56;
 206 CHECKREG r5, 0x00000000;
 207 CHECKREG r6, 0x00000000;
 208 CHECKREG r7, 0xFFFF0001;
 209
 210
 211
 212 pass