1 //Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp
2 // Spec Reference: dsp32mac dr a0 iu (unsigned int)
5 .include "testutils.inc"
13 // The result accumulated in A , and stored to a reg half
22 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
24 A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L );
26 A1 = R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H );
28 A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H );
30 CHECKREG r0, 0x8354FF22;
31 CHECKREG r1, 0xFF221DD6;
32 CHECKREG r2, 0xC794315B;
33 CHECKREG r3, 0x315B6A18;
34 CHECKREG r4, 0xEFB72AE5;
35 CHECKREG r5, 0x2AE51252;
36 CHECKREG r6, 0xE00C32D9;
37 CHECKREG r7, 0x32D896FE;
39 // The result accumulated in A , and stored to a reg half (MNOP)
48 R0.L = ( A0 = R1.L * R0.L );
50 R2.L = ( A0 += R2.L * R3.H );
52 R4.L = ( A0 -= R4.H * R5.L );
54 R6.L = ( A0 = R6.H * R7.H );
56 CHECKREG r0, 0xC554011F;
57 CHECKREG r1, 0x011EBDD6;
58 CHECKREG r2, 0xA1B5CB1B;
59 CHECKREG r3, 0xCB1A8C3C;
60 CHECKREG r4, 0xCFBCB741;
61 CHECKREG r5, 0xB741151C;
62 CHECKREG r6, 0xE50CEA3C;
63 CHECKREG r7, 0xEA3BDCD0;
65 // The result accumulated in A , and stored to a reg half (MNOP)
74 R0.L = ( A0 -= R1.L * R0.L );
76 R2.L = ( A0 = R2.H * R3.L );
78 R4.L = ( A0 = R4.H * R5.H );
80 R6.L = ( A0 += R6.L * R7.H );
82 CHECKREG r0, 0x4B54D842;
83 CHECKREG r1, 0xD841BEFA;
84 CHECKREG r2, 0xA4BB3906;
85 CHECKREG r3, 0x3906223A;
86 CHECKREG r4, 0x9F4B46DE;
87 CHECKREG r5, 0x46DDA278;
88 CHECKREG r6, 0xB00C26E0;
89 CHECKREG r7, 0x26E036AC;
91 // The result accumulated in A , and stored to a reg half
100 A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L );
102 A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L );
104 A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H );
106 A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H );
108 CHECKREG r0, 0x1A544DFA;
109 CHECKREG r1, 0x4DFA5880;
110 CHECKREG r2, 0xC13F2602;
111 CHECKREG r3, 0x26025482;
112 CHECKREG r4, 0xAFCC1CAD;
113 CHECKREG r5, 0x1CAD17A0;
114 CHECKREG r6, 0xC00C4F71;
115 CHECKREG r7, 0x4F70B886;