sim/testsuite/sim/bfin/c_dsp32alu_abs.s

   1 //Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp
   2 // Spec Reference: dsp32alu dregs = abs ( dregs, dregs)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0x15678911;
  12 imm32 r1, 0x2789ab1d;
  13 imm32 r2, 0x34445515;
  14 imm32 r3, 0x46667717;
  15 imm32 r4, 0x5567891b;
  16 imm32 r5, 0x6789ab1d;
  17 imm32 r6, 0x74445515;
  18 imm32 r7, 0x86667777;
  19 R0 = ABS R0;
  20 R1 = ABS R1;
  21 R2 = ABS R2;
  22 R3 = ABS R3;
  23 R4 = ABS R4;
  24 R5 = ABS R5;
  25 R6 = ABS R6;
  26 R7 = ABS R7;
  27 CHECKREG r0, 0x15678911;
  28 CHECKREG r1, 0x2789AB1D;
  29 CHECKREG r2, 0x34445515;
  30 CHECKREG r3, 0x46667717;
  31 CHECKREG r4, 0x5567891B;
  32 CHECKREG r5, 0x6789AB1D;
  33 CHECKREG r6, 0x74445515;
  34 CHECKREG r7, 0x79998889;
  35
  36 imm32 r0, 0x9567892b;
  37 imm32 r1, 0xa789ab2d;
  38 imm32 r2, 0xb4445525;
  39 imm32 r3, 0xc6667727;
  40 imm32 r4, 0xd8889929;
  41 imm32 r5, 0xeaaabb2b;
  42 imm32 r6, 0xfcccdd2d;
  43 imm32 r7, 0x0eeeffff;
  44 R0 = ABS R7;
  45 R1 = ABS R6;
  46 R2 = ABS R5;
  47 R3 = ABS R4;
  48 R4 = ABS R3;
  49 R5 = ABS R2;
  50 R6 = ABS R1;
  51 R7 = ABS R0;
  52 CHECKREG r0, 0x0EEEFFFF;
  53 CHECKREG r1, 0x033322D3;
  54 CHECKREG r2, 0x155544D5;
  55 CHECKREG r3, 0x277766D7;
  56 CHECKREG r4, 0x277766D7;
  57 CHECKREG r5, 0x155544D5;
  58 CHECKREG r6, 0x033322D3;
  59 CHECKREG r7, 0x0EEEFFFF;
  60
  61
  62 pass