1 //Original:/proj/frio/dv/testcases/core/c_compi2opd_flags/c_compi2opd_flags.dsp
2 // Spec Reference: compi2opd dregs += imm7 flags (az, an, ac, av0)
6 .include "testutils.inc"
10 ASTAT = R0; // initialize astat
14 R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0
16 R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0
18 R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0
21 R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0
23 R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0
25 CHECKREG r0, 0x00000000;
26 CHECKREG r1, 0x00000000;
27 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
29 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
30 CHECKREG r6, 0x00000000;
35 R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0
38 R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0
40 R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0
42 CHECKREG r0, 0xFFFFFFFF;
43 CHECKREG r1, 0x00000000;
46 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
50 R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1
53 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1
56 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0
58 CHECKREG r0, 0x7FFFFFFE;
59 CHECKREG r1, 0x80000000;
60 CHECKREG r2, 0x7FFFFFFF;
61 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
62 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); //C
63 CHECKREG r7, (_VS|_V|_V_COPY|_AN); // A
65 // AZ, AN, AC, AV0 for R0
69 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1
72 R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1
75 R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0
77 CHECKREG r0, 0x80000001;
78 CHECKREG r1, 0x7FFFFFFF;
79 CHECKREG r2, 0x80000000;
80 CHECKREG r5, (_VS|_AN);
81 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
82 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
88 R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0
90 R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0
92 R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0
95 R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0
97 R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0
99 CHECKREG r0, 0x00000000;
100 CHECKREG r1, 0x00000000;
101 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
103 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
104 CHECKREG r6, 0x00000000;
108 imm32 r1, 0xffffffff;
109 R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0
112 R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0
114 R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0
116 CHECKREG r0, 0x00000000;
117 CHECKREG r1, 0xFFFFFFFF;
120 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
123 imm32 r1, 0x7fffffff;
124 R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1
127 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1
130 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0
132 CHECKREG r0, 0x80000000;
133 CHECKREG r1, 0x7FFFFFFE;
134 CHECKREG r2, 0x7FFFFFFF;
135 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
136 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
137 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
139 // AZ, AN, AC, AV0 for R1
142 imm32 r1, 0x80000000;
143 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1
146 R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1
149 R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0
151 CHECKREG r0, 0x7FFFFFFF;
152 CHECKREG r1, 0x80000001;
153 CHECKREG r2, 0x80000000;
154 CHECKREG r5, (_VS|_AN);
155 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
156 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
159 imm32 r2, 0x00000000;
161 R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0
163 R2 += 1; // az = 0 an = 0 ac = 0 av0 = 0
165 R2 += -1; // az = 1 an = 0 ac = 1 av0 = 0
168 R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0
170 R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0
172 CHECKREG r1, 0x00000000;
173 CHECKREG r2, 0x00000000;
174 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
176 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
177 CHECKREG r6, 0x00000000;
181 imm32 r2, 0xffffffff;
182 R2 += 1; // az = 1 an = 0 ac = 1 av0 = 0
185 R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0
187 R2 += -1; // az = 0 an = 1 ac = 0 av0 = 0
189 CHECKREG r2, 0xFFFFFFFF;
190 CHECKREG r1, 0x00000000;
193 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
196 imm32 r2, 0x7fffffff;
197 R2 += 1; // az = 0 an = 1 ac = 0 av0 = 1
200 R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1
203 R2 += -1; // az = 0 an = 0 ac = 1 av0 = 0
205 CHECKREG r0, 0x80000000;
206 CHECKREG r1, 0x7FFFFFFF;
207 CHECKREG r2, 0x7FFFFFFE;
208 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
209 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
210 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
212 // AZ, AN, AC, AV0 for R2
215 imm32 r2, 0x80000000;
216 R2 += -1; // az = 0 an = 0 ac = 1 av0 = 1
219 R2 += 1; // az = 1 an = 1 ac = 0 av0 = 1
222 R2 += 1; // az = 0 an = 1 ac = 0 av0 = 0
224 CHECKREG r0, 0x7FFFFFFF;
225 CHECKREG r1, 0x80000000;
226 CHECKREG r2, 0x80000001;
227 CHECKREG r5, (_VS|_AN);
228 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
229 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
232 imm32 r3, 0x00000000;
234 R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0
236 R3 += 1; // az = 0 an = 0 ac = 0 av0 = 0
238 R3 += -1; // az = 1 an = 0 ac = 1 av0 = 0
241 R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0
243 R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0
245 CHECKREG r0, 0x00000000;
246 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
247 CHECKREG r3, 0x00000000;
249 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
250 CHECKREG r6, 0x00000000;
254 imm32 r3, 0xffffffff;
255 R3 += 1; // az = 1 an = 0 ac = 1 av0 = 0
258 R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0
260 R3 += -1; // az = 0 an = 1 ac = 0 av0 = 0
262 CHECKREG r0, 0x00000000;
263 CHECKREG r3, 0xFFFFFFFF;
266 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
269 imm32 r3, 0x7fffffff;
270 R3 += 1; // az = 0 an = 1 ac = 0 av0 = 1
273 R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1
276 R3 += -1; // az = 0 an = 0 ac = 1 av0 = 0
278 CHECKREG r0, 0x80000000;
279 CHECKREG r1, 0x7FFFFFFF;
280 CHECKREG r3, 0x7FFFFFFE;
281 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
282 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
283 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
285 // AZ, AN, AC, AV0 for R3
288 imm32 r3, 0x80000000;
289 R3 += -1; // az = 0 an = 0 ac = 1 av0 = 1
292 R3 += 1; // az = 1 an = 1 ac = 0 av0 = 1
295 R3 += 1; // az = 0 an = 1 ac = 0 av0 = 0
297 CHECKREG r0, 0x7FFFFFFF;
298 CHECKREG r1, 0x80000000;
299 CHECKREG r3, 0x80000001;
300 CHECKREG r5, (_VS|_AN);
301 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
302 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
305 imm32 r4, 0x00000000;
307 R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0
309 R4 += 1; // az = 0 an = 0 ac = 0 av0 = 0
311 R4 += -1; // az = 1 an = 0 ac = 1 av0 = 0
314 R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0
316 R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0
318 CHECKREG r1, 0x00000000;
319 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
321 CHECKREG r4, 0x00000000;
322 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
323 CHECKREG r6, 0x00000000;
327 imm32 r4, 0xffffffff;
328 R4 += 1; // az = 1 an = 0 ac = 1 av0 = 0
331 R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0
333 R4 += -1; // az = 0 an = 1 ac = 0 av0 = 0
335 CHECKREG r1, 0x00000000;
336 CHECKREG r4, 0xFFFFFFFF;
339 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
342 imm32 r4, 0x7fffffff;
343 R4 += 1; // az = 0 an = 1 ac = 0 av0 = 1
346 R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1
349 R4 += -1; // az = 0 an = 0 ac = 1 av0 = 0
351 CHECKREG r1, 0x80000000;
352 CHECKREG r2, 0x7FFFFFFF;
353 CHECKREG r4, 0x7FFFFFFE;
354 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
355 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
356 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
358 // AZ, AN, AC, AV0 for R4
361 imm32 r4, 0x80000000;
362 R4 += -1; // az = 0 an = 0 ac = 1 av0 = 1
365 R4 += 1; // az = 1 an = 1 ac = 0 av0 = 1
368 R4 += 1; // az = 0 an = 1 ac = 0 av0 = 0
370 CHECKREG r1, 0x7FFFFFFF;
371 CHECKREG r2, 0x80000000;
372 CHECKREG r4, 0x80000001;
373 CHECKREG r5, (_VS|_AN);
374 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
375 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
378 imm32 r5, 0x00000000;
380 R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0
382 R5 += 1; // az = 0 an = 0 ac = 0 av0 = 0
384 R5 += -1; // az = 1 an = 0 ac = 1 av0 = 0
387 R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0
389 R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0
391 CHECKREG r0, 0x00000000;
392 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
393 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
395 CHECKREG r5, 0x00000000;
396 CHECKREG r6, 0x00000000;
400 imm32 r5, 0xffffffff;
401 R5 += 1; // az = 1 an = 0 ac = 1 av0 = 0
404 R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0
406 R5 += -1; // az = 0 an = 1 ac = 0 av0 = 0
408 CHECKREG r0, 0x00000000;
410 CHECKREG r5, 0xFFFFFFFF;
412 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
415 imm32 r5, 0x7fffffff;
416 R5 += 1; // az = 0 an = 1 ac = 0 av0 = 1
419 R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1
422 R5 += -1; // az = 0 an = 0 ac = 1 av0 = 0
424 CHECKREG r0, 0x80000000;
425 CHECKREG r2, 0x7FFFFFFF;
426 CHECKREG r4, (_VS|_AC0|_AC0_COPY);
427 CHECKREG r5, 0x7FFFFFFE;
428 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
429 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
431 // AZ, AN, AC, AV0 for R5
434 imm32 r5, 0x80000000;
435 R5 += -1; // az = 0 an = 0 ac = 1 av0 = 1
438 R5 += 1; // az = 1 an = 1 ac = 0 av0 = 1
441 R5 += 1; // az = 0 an = 1 ac = 0 av0 = 0
443 CHECKREG r0, 0x7FFFFFFF;
444 CHECKREG r2, 0x80000000;
445 CHECKREG r4, (_VS|_AN);
446 CHECKREG r5, 0x80000001;
447 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
448 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
451 imm32 r6, 0x00000000;
453 R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0
455 R6 += 1; // az = 0 an = 0 ac = 0 av0 = 0
457 R6 += -1; // az = 1 an = 0 ac = 1 av0 = 0
460 R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0
462 R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0
464 CHECKREG r0, 0x00000000;
465 CHECKREG r1, 0x00000000;
466 CHECKREG r3, (_AC0|_AC0_COPY|_AZ);
468 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
469 CHECKREG r6, 0x00000000;
473 imm32 r6, 0xffffffff;
474 R6 += 1; // az = 1 an = 0 ac = 1 av0 = 0
477 R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0
479 R6 += -1; // az = 0 an = 1 ac = 0 av0 = 0
481 CHECKREG r1, 0x00000000;
484 CHECKREG r6, 0xFFFFFFFF;
485 CHECKREG r7, (_AC0|_AC0_COPY|_AZ);
490 imm32 r6, 0x7fffffff;
491 R6 += 1; // az = 0 an = 1 ac = 0 av0 = 1
494 R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1
497 R6 += -1; // az = 0 an = 0 ac = 1 av0 = 0
499 CHECKREG r0, 0x80000000;
500 CHECKREG r1, 0x7FFFFFFF;
501 CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
502 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
503 CHECKREG r6, 0x7FFFFFFE;
504 CHECKREG r7, (_VS|_V|_V_COPY|_AN);
506 // AZ, AN, AC, AV0 for R6
509 imm32 r6, 0x80000000;
510 R6 += -1; // az = 0 an = 0 ac = 1 av0 = 1
513 R6 += 1; // az = 1 an = 1 ac = 0 av0 = 1
516 R6 += 1; // az = 0 an = 1 ac = 0 av0 = 0
518 CHECKREG r0, 0x7FFFFFFF;
519 CHECKREG r1, 0x80000000;
520 CHECKREG r4, (_VS|_V|_V_COPY|_AN);
521 CHECKREG r5, (_VS|_AN);
522 CHECKREG r6, 0x80000001;
523 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
526 imm32 r7, 0x00000000;
528 R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0
530 R7 += 1; // az = 0 an = 0 ac = 0 av0 = 0
532 R7 += -1; // az = 1 an = 0 ac = 1 av0 = 0
535 R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0
537 R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0
539 CHECKREG r0, 0x00000000;
541 CHECKREG r2, (_AC0|_AC0_COPY|_AZ);
543 CHECKREG r5, (_AC0|_AC0_COPY|_AZ);
544 CHECKREG r6, 0x00000000;
545 CHECKREG r7, 0x00000000;
548 imm32 r7, 0xffffffff;
549 R7 += 1; // az = 1 an = 0 ac = 1 av0 = 0
552 R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0
554 R7 += -1; // az = 0 an = 1 ac = 0 av0 = 0
556 CHECKREG r0, 0x00000000;
557 CHECKREG r4, (_AC0|_AC0_COPY|_AZ);
560 CHECKREG r7, 0xFFFFFFFF;
565 imm32 r7, 0x7fffffff;
566 R7 += 1; // az = 0 an = 1 ac = 0 av0 = 1
569 R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1
572 R7 += -1; // az = 0 an = 0 ac = 1 av0 = 0
574 CHECKREG r0, 0x80000000;
575 CHECKREG r1, 0x7FFFFFFF;
576 CHECKREG r4, (_VS|_V|_V_COPY|_AN);
577 CHECKREG r5, (_VS|_AC0|_AC0_COPY);
578 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
579 CHECKREG r7, 0x7FFFFFFE;
581 // AZ, AN, AC, AV0 for R7
584 imm32 r7, 0x80000000;
585 R7 += -1; // az = 0 an = 0 ac = 1 av0 = 1
588 R7 += 1; // az = 1 an = 1 ac = 0 av0 = 1
591 R7 += 1; // az = 0 an = 1 ac = 0 av0 = 0
593 CHECKREG r0, 0x7FFFFFFF;
594 CHECKREG r1, 0x80000000;
595 CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY);
596 CHECKREG r5, (_VS|_AN);
597 CHECKREG r6, (_VS|_V|_V_COPY|_AN);
598 CHECKREG r7, 0x80000001;