Add support to GDB for the Renesas rl78 architecture.
[external/binutils.git] / sim / testsuite / sim / bfin / c_brcc_brf_brt_nbp.s
1 //Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp
2 // Spec Reference: brcc brf brt no bp
3 # mach: bfin
4
5 .include "testutils.inc"
6         start
7
8
9
10
11 imm32 r0, 0x00000000;
12 imm32 r1, 0x00000000;
13 imm32 r2, 0x00000000;
14 imm32 r3, 0x00000000;
15 imm32 r4, 0x00000000;
16 imm32 r5, 0x00000000;
17 imm32 r6, 0x00000000;
18 imm32 r7, 0x00000000;
19
20 begin:
21         ASTAT = R0;             // clear cc
22         CC = ! CC;              // set cc=1
23         IF CC JUMP good1;       // branch on true (should branch)
24         R1 = 1;                 // if go here, error
25 good1:  IF !CC JUMP bad1;       // branch on false (should not branch)
26         JUMP.S good2;           // should branch here
27 bad1:   R2 = 2;                 // if go here, error
28 good2:  CC = ! CC;              // clear cc=0
29         IF !CC JUMP good3;      // branch on false (should branch)
30         R3 = 3;                 // if go here, error
31 good3:  IF CC JUMP bad2;        // branch on true (should not branch)
32         JUMP.S end;             // we're done
33 bad2:   R4 = 4;                 // if go here error
34
35 end:
36
37 CHECKREG r0, 0x00000000;
38 CHECKREG r1, 0x00000000;
39 CHECKREG r2, 0x00000000;
40 CHECKREG r3, 0x00000000;
41 CHECKREG r4, 0x00000000;
42 CHECKREG r5, 0x00000000;
43 CHECKREG r6, 0x00000000;
44 CHECKREG r7, 0x00000000;
45
46 pass