1 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
3 * s390-opc.txt (flogr): Require a register pair destination.
5 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
7 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
10 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
12 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
14 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
16 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
17 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
18 XLS_MASK, PPCVSX2): New defines.
19 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
20 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
21 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
22 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
23 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
24 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
25 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
26 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
27 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
28 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
29 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
30 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
31 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
32 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
33 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
34 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
35 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
36 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
37 <lxvx, stxvx>: New extended mnemonics.
39 2013-05-17 Alan Modra <amodra@gmail.com>
41 * ia64-raw.tbl: Replace non-ASCII char.
42 * ia64-waw.tbl: Likewise.
43 * ia64-asmtab.c: Regenerate.
45 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
47 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
48 * i386-init.h: Regenerated.
50 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
52 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
53 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
54 check from [0, 255] to [-128, 255].
56 2013-05-09 Andrew Pinski <apinski@cavium.com>
58 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
59 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
60 (parse_mips_dis_option): Handle the virt option.
61 (print_insn_args): Handle "+J".
62 (print_mips_disassembler_options): Print out message about virt64.
63 * mips-opc.c (IVIRT): New define.
64 (IVIRT64): New define.
65 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
66 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
67 Move rfe to the bottom as it conflicts with tlbgp.
69 2013-05-09 Alan Modra <amodra@gmail.com>
71 * ppc-opc.c (extract_vlesi): Properly sign extend.
72 (extract_vlensi): Likewise. Comment reason for setting invalid.
74 2013-05-02 Nick Clifton <nickc@redhat.com>
76 * msp430-dis.c: Add support for MSP430X instructions.
78 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
80 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
83 2013-04-17 Wei-chen Wang <cole945@gmail.com>
86 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
88 (hash_insns_list): Likewise.
90 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
92 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
95 2013-04-08 Jan Beulich <jbeulich@suse.com>
97 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
98 * i386-tbl.h: Re-generate.
100 2013-04-06 David S. Miller <davem@davemloft.net>
102 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
103 of an opcode, prefer the one with F_PREFERRED set.
104 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
105 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
106 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
107 mark existing mnenomics as aliases. Add "cc" suffix to edge
108 instructions generating condition codes, mark existing mnenomics
109 as aliases. Add "fp" prefix to VIS compare instructions, mark
110 existing mnenomics as aliases.
112 2013-04-03 Nick Clifton <nickc@redhat.com>
114 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
115 destination address by subtracting the operand from the current
117 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
118 a positive value in the insn.
119 (extract_u16_loop): Do not negate the returned value.
120 (D16_LOOP): Add V850_INVERSE_PCREL flag.
122 (ceilf.sw): Remove duplicate entry.
123 (cvtf.hs): New entry.
129 (maddf.s): Restrict to E3V5 architectures.
131 (nmaddf.s): Likewise.
132 (nmsubf.s): Likewise.
134 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
136 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
138 (print_insn): Pass sizeflag to get_sib.
140 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
143 * tic6x-dis.c: Add support for displaying 16-bit insns.
145 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
148 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
149 individual msb and lsb halves in src1 & src2 fields. Discard the
150 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
151 follow what Ti SDK does in that case as any value in the src1
152 field yields the same output with SDK disassembler.
154 2013-03-12 Michael Eager <eager@eagercon.com>
156 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
158 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
160 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
162 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
164 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
166 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
168 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
170 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
172 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
173 (thumb32_opcodes): Likewise.
174 (print_insn_thumb32): Handle 'S' control char.
176 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
178 * lm32-desc.c: Regenerate.
180 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
182 * i386-reg.tbl (riz): Add RegRex64.
183 * i386-tbl.h: Regenerated.
185 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
187 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
188 (aarch64_feature_crc): New static.
190 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
191 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
192 * aarch64-asm-2.c: Re-generate.
193 * aarch64-dis-2.c: Ditto.
194 * aarch64-opc-2.c: Ditto.
196 2013-02-27 Alan Modra <amodra@gmail.com>
198 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
199 * rl78-decode.c: Regenerate.
201 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
203 * rl78-decode.opc: Fix encoding of DIVWU insn.
204 * rl78-decode.c: Regenerate.
206 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
209 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
211 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
212 (cpu_flags): Add CpuSMAP.
214 * i386-opc.h (CpuSMAP): New.
215 (i386_cpu_flags): Add cpusmap.
217 * i386-opc.tbl: Add clac and stac.
219 * i386-init.h: Regenerated.
220 * i386-tbl.h: Likewise.
222 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
224 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
225 which also makes the disassembler output be in little
226 endian like it should be.
228 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
230 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
232 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
234 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
236 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
237 section disassembled.
239 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
241 * arm-dis.c: Update strht pattern.
243 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
245 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
246 single-float. Disable ll, lld, sc and scd for EE. Disable the
247 trunc.w.s macro for EE.
249 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
250 Andrew Jenner <andrew@codesourcery.com>
252 Based on patches from Altera Corporation.
254 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
256 * Makefile.in: Regenerated.
257 * configure.in: Add case for bfd_nios2_arch.
258 * configure: Regenerated.
259 * disassemble.c (ARCH_nios2): Define.
260 (disassembler): Add case for bfd_arch_nios2.
261 * nios2-dis.c: New file.
262 * nios2-opc.c: New file.
264 2013-02-04 Alan Modra <amodra@gmail.com>
266 * po/POTFILES.in: Regenerate.
267 * rl78-decode.c: Regenerate.
268 * rx-decode.c: Regenerate.
270 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
272 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
273 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
274 * aarch64-asm.c (convert_xtl_to_shll): New function.
275 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
276 calling convert_xtl_to_shll.
277 * aarch64-dis.c (convert_shll_to_xtl): New function.
278 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
279 calling convert_shll_to_xtl.
280 * aarch64-gen.c: Update copyright year.
281 * aarch64-asm-2.c: Re-generate.
282 * aarch64-dis-2.c: Re-generate.
283 * aarch64-opc-2.c: Re-generate.
285 2013-01-24 Nick Clifton <nickc@redhat.com>
287 * v850-dis.c: Add support for e3v5 architecture.
288 * v850-opc.c: Likewise.
290 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
292 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
293 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
294 * aarch64-opc.c (operand_general_constraint_met_p): For
295 AARCH64_MOD_LSL, move the range check on the shift amount before the
296 alignment check; change to call set_sft_amount_out_of_range_error
297 instead of set_imm_out_of_range_error.
298 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
299 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
300 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
303 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
305 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
307 * i386-init.h: Regenerated.
308 * i386-tbl.h: Likewise.
310 2013-01-15 Nick Clifton <nickc@redhat.com>
312 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
314 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
316 2013-01-14 Will Newton <will.newton@imgtec.com>
318 * metag-dis.c (REG_WIDTH): Increase to 64.
320 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
322 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
323 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
324 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
326 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
327 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
328 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
329 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
331 2013-01-10 Will Newton <will.newton@imgtec.com>
333 * Makefile.am: Add Meta.
334 * configure.in: Add Meta.
335 * disassemble.c: Add Meta support.
336 * metag-dis.c: New file.
337 * Makefile.in: Regenerate.
338 * configure: Regenerate.
340 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
342 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
343 (match_opcode): Rename to cr16_match_opcode.
345 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
347 * mips-dis.c: Add names for CP0 registers of r5900.
348 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
349 instructions sq and lq.
350 Add support for MIPS r5900 CPU.
351 Add support for 128 bit MMI (Multimedia Instructions).
352 Add support for EE instructions (Emotion Engine).
353 Disable unsupported floating point instructions (64 bit and
354 undefined compare operations).
355 Enable instructions of MIPS ISA IV which are supported by r5900.
356 Disable 64 bit co processor instructions.
357 Disable 64 bit multiplication and division instructions.
358 Disable instructions for co-processor 2 and 3, because these are
359 not supported (preparation for later VU0 support (Vector Unit)).
360 Disable cvt.w.s because this behaves like trunc.w.s and the
361 correct execution can't be ensured on r5900.
362 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
363 will confuse less developers and compilers.
365 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
367 * aarch64-opc.c (aarch64_print_operand): Change to print
368 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
370 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
371 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
374 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
376 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
377 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
379 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
381 * i386-gen.c (process_copyright): Update copyright year to 2013.
383 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
385 * cr16-dis.c (match_opcode,make_instruction): Remove static
387 (dwordU,wordU): Moved typedefs to opcode/cr16.h
388 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
390 For older changes see ChangeLog-2012
392 Copyright (C) 2013 Free Software Foundation, Inc.
394 Copying and distribution of this file, with or without modification,
395 are permitted in any medium without royalty provided the copyright
396 notice and this notice are preserved.
402 version-control: never