1 2016-07-01 Tristan Gingold <gingold@adacore.com>
3 * configure: Regenerate.
5 2016-07-01 Jan Beulich <jbeulich@suse.com>
7 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
8 (movzb): Adjust to cover all permitted suffixes.
10 * i386-tbl.h: Re-generate.
12 2016-07-01 Jan Beulich <jbeulich@suse.com>
14 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
15 (lgdt): Remove Tbyte from non-64-bit variant.
16 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
17 xsaves64, xsavec64): Remove Disp16.
18 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
19 Remove Disp32S from non-64-bit variants. Remove Disp16 from
21 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
22 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
23 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
25 * i386-tbl.h: Re-generate.
27 2016-07-01 Jan Beulich <jbeulich@suse.com>
29 * i386-opc.tbl (xlat): Remove RepPrefixOk.
30 * i386-tbl.h: Re-generate.
32 2016-06-30 Yao Qi <yao.qi@linaro.org>
34 * arm-dis.c (print_insn): Fix typo in comment.
36 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
38 * aarch64-opc.c (operand_general_constraint_met_p): Check the
39 range of ldst_elemlist operands.
40 (print_register_list): Use PRIi64 to print the index.
41 (aarch64_print_operand): Likewise.
43 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
45 * mcore-opc.h: Remove sentinal.
46 * mcore-dis.c (print_insn_mcore): Adjust.
48 2016-06-23 Graham Markall <graham.markall@embecosm.com>
50 * arc-opc.c: Correct description of availability of NPS400
53 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
55 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
56 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
57 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
59 <setb>: Change to a VX form instruction.
60 (insert_sh6): Add support for rldixor.
61 (extract_sh6): Likewise.
63 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
65 * arc-ext.h: Wrap in extern C.
67 2016-06-21 Graham Markall <graham.markall@embecosm.com>
69 * arc-dis.c (arc_insn_length): Add comment on instruction length.
70 Use same method for determining instruction length on ARC700 and
72 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
73 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
74 with the NPS400 subclass.
75 * arc-opc.c: Likewise.
77 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
79 * sparc-opc.c (rdasr): New macro.
85 (sparc_opcodes): Use the macros above to fix and expand the
86 definition of read/write instructions from/to
87 asr/privileged/hyperprivileged instructions.
88 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
89 %hva_mask_nz. Prefer softint_set and softint_clear over
90 set_softint and clear_softint.
91 (print_insn_sparc): Support %ver in Rd.
93 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
95 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
96 architecture according to the hardware capabilities they require.
98 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
100 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
101 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
102 bfd_mach_sparc_v9{c,d,e,v,m}.
103 * sparc-opc.c (MASK_V9C): Define.
104 (MASK_V9D): Likewise.
105 (MASK_V9E): Likewise.
106 (MASK_V9V): Likewise.
107 (MASK_V9M): Likewise.
108 (v6): Add MASK_V9{C,D,E,V,M}.
109 (v6notlet): Likewise.
113 (v9andleon): Likewise.
121 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
123 2016-06-15 Nick Clifton <nickc@redhat.com>
125 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
126 constants to match expected behaviour.
127 (nds32_parse_opcode): Likewise. Also for whitespace.
129 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
131 * arc-opc.c (extract_rhv1): Extract value from insn.
133 2016-06-14 Graham Markall <graham.markall@embecosm.com>
135 * arc-nps400-tbl.h: Add ldbit instruction.
136 * arc-opc.c: Add flag classes required for ldbit.
138 2016-06-14 Graham Markall <graham.markall@embecosm.com>
140 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
141 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
142 support the above instructions.
144 2016-06-14 Graham Markall <graham.markall@embecosm.com>
146 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
147 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
148 csma, cbba, zncv, and hofs.
149 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
150 support the above instructions.
152 2016-06-06 Graham Markall <graham.markall@embecosm.com>
154 * arc-nps400-tbl.h: Add andab and orab instructions.
156 2016-06-06 Graham Markall <graham.markall@embecosm.com>
158 * arc-nps400-tbl.h: Add addl-like instructions.
160 2016-06-06 Graham Markall <graham.markall@embecosm.com>
162 * arc-nps400-tbl.h: Add mxb and imxb instructions.
164 2016-06-06 Graham Markall <graham.markall@embecosm.com>
166 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
169 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
171 * s390-dis.c (option_use_insn_len_bits_p): New file scope
173 (init_disasm): Handle new command line option "insnlength".
174 (print_s390_disassembler_options): Mention new option in help
176 (print_insn_s390): Use the encoded insn length when dumping
177 unknown instructions.
179 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
181 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
182 to the address and set as symbol address for LDS/ STS immediate operands.
184 2016-06-07 Alan Modra <amodra@gmail.com>
186 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
187 cpu for "vle" to e500.
188 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
189 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
190 (PPCNONE): Delete, substitute throughout.
191 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
192 except for major opcode 4 and 31.
193 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
195 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
197 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
198 ARM_EXT_RAS in relevant entries.
200 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
203 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
206 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
209 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
211 Add comments for '&'.
212 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
214 (intel_operand_size): Handle indir_v_mode.
215 (OP_E_register): Likewise.
216 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
217 64-bit indirect call/jmp for AMD64.
218 * i386-tbl.h: Regenerated
220 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
222 * arc-dis.c (struct arc_operand_iterator): New structure.
223 (find_format_from_table): All the old content from find_format,
224 with some minor adjustments, and parameter renaming.
225 (find_format_long_instructions): New function.
226 (find_format): Rewritten.
227 (arc_insn_length): Add LSB parameter.
228 (extract_operand_value): New function.
229 (operand_iterator_next): New function.
230 (print_insn_arc): Use new functions to find opcode, and iterator
232 * arc-opc.c (insert_nps_3bit_dst_short): New function.
233 (extract_nps_3bit_dst_short): New function.
234 (insert_nps_3bit_src2_short): New function.
235 (extract_nps_3bit_src2_short): New function.
236 (insert_nps_bitop1_size): New function.
237 (extract_nps_bitop1_size): New function.
238 (insert_nps_bitop2_size): New function.
239 (extract_nps_bitop2_size): New function.
240 (insert_nps_bitop_mod4_msb): New function.
241 (extract_nps_bitop_mod4_msb): New function.
242 (insert_nps_bitop_mod4_lsb): New function.
243 (extract_nps_bitop_mod4_lsb): New function.
244 (insert_nps_bitop_dst_pos3_pos4): New function.
245 (extract_nps_bitop_dst_pos3_pos4): New function.
246 (insert_nps_bitop_ins_ext): New function.
247 (extract_nps_bitop_ins_ext): New function.
248 (arc_operands): Add new operands.
249 (arc_long_opcodes): New global array.
250 (arc_num_long_opcodes): New global.
251 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
253 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
255 * nds32-asm.h: Add extern "C".
256 * sh-opc.h: Likewise.
258 2016-06-01 Graham Markall <graham.markall@embecosm.com>
260 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
261 0,b,limm to the rflt instruction.
263 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
265 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
268 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
271 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
272 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
273 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
274 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
275 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
276 * i386-init.h: Regenerated.
278 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
281 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
282 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
283 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
284 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
285 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
286 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
287 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
288 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
289 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
290 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
291 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
292 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
293 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
294 CpuRegMask for AVX512.
295 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
297 (set_bitfield_from_cpu_flag_init): New function.
298 (set_bitfield): Remove const on f. Call
299 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
300 * i386-opc.h (CpuRegMMX): New.
301 (CpuRegXMM): Likewise.
302 (CpuRegYMM): Likewise.
303 (CpuRegZMM): Likewise.
304 (CpuRegMask): Likewise.
305 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
307 * i386-init.h: Regenerated.
308 * i386-tbl.h: Likewise.
310 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
313 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
314 (opcode_modifiers): Add AMD64 and Intel64.
315 (main): Properly verify CpuMax.
316 * i386-opc.h (CpuAMD64): Removed.
317 (CpuIntel64): Likewise.
318 (CpuMax): Set to CpuNo64.
319 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
322 (i386_opcode_modifier): Add amd64 and intel64.
323 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
325 * i386-init.h: Regenerated.
326 * i386-tbl.h: Likewise.
328 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
331 * i386-gen.c (main): Fail if CpuMax is incorrect.
332 * i386-opc.h (CpuMax): Set to CpuIntel64.
333 * i386-tbl.h: Regenerated.
335 2016-05-27 Nick Clifton <nickc@redhat.com>
338 * msp430-dis.c (msp430dis_read_two_bytes): New function.
339 (msp430dis_opcode_unsigned): New function.
340 (msp430dis_opcode_signed): New function.
341 (msp430_singleoperand): Use the new opcode reading functions.
342 Only disassenmble bytes if they were successfully read.
343 (msp430_doubleoperand): Likewise.
344 (msp430_branchinstr): Likewise.
345 (msp430x_callx_instr): Likewise.
346 (print_insn_msp430): Check that it is safe to read bytes before
347 attempting disassembly. Use the new opcode reading functions.
349 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
351 * ppc-opc.c (CY): New define. Document it.
352 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
354 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
356 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
357 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
358 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
359 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
361 * i386-init.h: Regenerated.
363 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
366 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
367 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
368 * i386-init.h: Regenerated.
370 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
372 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
373 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
374 * i386-init.h: Regenerated.
376 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
378 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
380 (print_insn_arc): Set insn_type information.
381 * arc-opc.c (C_CC): Add F_CLASS_COND.
382 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
383 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
384 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
385 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
386 (brne, brne_s, jeq_s, jne_s): Likewise.
388 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
390 * arc-tbl.h (neg): New instruction variant.
392 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
394 * arc-dis.c (find_format, find_format, get_auxreg)
395 (print_insn_arc): Changed.
396 * arc-ext.h (INSERT_XOP): Likewise.
398 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
400 * tic54x-dis.c (sprint_mmr): Adjust.
401 * tic54x-opc.c: Likewise.
403 2016-05-19 Alan Modra <amodra@gmail.com>
405 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
407 2016-05-19 Alan Modra <amodra@gmail.com>
409 * ppc-opc.c: Formatting.
410 (NSISIGNOPT): Define.
411 (powerpc_opcodes <subis>): Use NSISIGNOPT.
413 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
415 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
416 replacing references to `micromips_ase' throughout.
417 (_print_insn_mips): Don't use file-level microMIPS annotation to
418 determine the disassembly mode with the symbol table.
420 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
422 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
424 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
426 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
428 * mips-opc.c (D34): New macro.
429 (mips_builtin_opcodes): Define bposge32c for DSPr3.
431 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
433 * i386-dis.c (prefix_table): Add RDPID instruction.
434 * i386-gen.c (cpu_flag_init): Add RDPID flag.
435 (cpu_flags): Add RDPID bitfield.
436 * i386-opc.h (enum): Add RDPID element.
437 (i386_cpu_flags): Add RDPID field.
438 * i386-opc.tbl: Add RDPID instruction.
439 * i386-init.h: Regenerate.
440 * i386-tbl.h: Regenerate.
442 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
444 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
445 branch type of a symbol.
446 (print_insn): Likewise.
448 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
450 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
451 Mainline Security Extensions instructions.
452 (thumb_opcodes): Add entries for narrow ARMv8-M Security
453 Extensions instructions.
454 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
456 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
459 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
461 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
463 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
465 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
466 (arcExtMap_genOpcode): Likewise.
467 * arc-opc.c (arg_32bit_rc): Define new variable.
468 (arg_32bit_u6): Likewise.
469 (arg_32bit_limm): Likewise.
471 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
473 * aarch64-gen.c (VERIFIER): Define.
474 * aarch64-opc.c (VERIFIER): Define.
475 (verify_ldpsw): Use static linkage.
476 * aarch64-opc.h (verify_ldpsw): Remove.
477 * aarch64-tbl.h: Use VERIFIER for verifiers.
479 2016-04-28 Nick Clifton <nickc@redhat.com>
482 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
483 * aarch64-opc.c (verify_ldpsw): New function.
484 * aarch64-opc.h (verify_ldpsw): New prototype.
485 * aarch64-tbl.h: Add initialiser for verifier field.
486 (LDPSW): Set verifier to verify_ldpsw.
488 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
492 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
493 smaller than address size.
495 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
497 * alpha-dis.c: Regenerate.
498 * crx-dis.c: Likewise.
499 * disassemble.c: Likewise.
500 * epiphany-opc.c: Likewise.
501 * fr30-opc.c: Likewise.
502 * frv-opc.c: Likewise.
503 * ip2k-opc.c: Likewise.
504 * iq2000-opc.c: Likewise.
505 * lm32-opc.c: Likewise.
506 * lm32-opinst.c: Likewise.
507 * m32c-opc.c: Likewise.
508 * m32r-opc.c: Likewise.
509 * m32r-opinst.c: Likewise.
510 * mep-opc.c: Likewise.
511 * mt-opc.c: Likewise.
512 * or1k-opc.c: Likewise.
513 * or1k-opinst.c: Likewise.
514 * tic80-opc.c: Likewise.
515 * xc16x-opc.c: Likewise.
516 * xstormy16-opc.c: Likewise.
518 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
520 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
521 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
522 calcsd, and calcxd instructions.
523 * arc-opc.c (insert_nps_bitop_size): Delete.
524 (extract_nps_bitop_size): Delete.
525 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
526 (extract_nps_qcmp_m3): Define.
527 (extract_nps_qcmp_m2): Define.
528 (extract_nps_qcmp_m1): Define.
529 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
530 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
531 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
532 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
533 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
536 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
538 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
540 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
542 * Makefile.in: Regenerated with automake 1.11.6.
543 * aclocal.m4: Likewise.
545 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
547 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
549 * arc-opc.c (insert_nps_cmem_uimm16): New function.
550 (extract_nps_cmem_uimm16): New function.
551 (arc_operands): Add NPS_XLDST_UIMM16 operand.
553 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
555 * arc-dis.c (arc_insn_length): New function.
556 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
557 (find_format): Change insnLen parameter to unsigned.
559 2016-04-13 Nick Clifton <nickc@redhat.com>
562 * v850-opc.c (v850_opcodes): Correct masks for long versions of
563 the LD.B and LD.BU instructions.
565 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
567 * arc-dis.c (find_format): Check for extension flags.
568 (print_flags): New function.
569 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
571 * arc-ext.c (arcExtMap_coreRegName): Use
572 LAST_EXTENSION_CORE_REGISTER.
573 (arcExtMap_coreReadWrite): Likewise.
574 (dump_ARC_extmap): Update printing.
575 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
576 (arc_aux_regs): Add cpu field.
577 * arc-regs.h: Add cpu field, lower case name aux registers.
579 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
581 * arc-tbl.h: Add rtsc, sleep with no arguments.
583 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
585 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
587 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
588 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
589 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
590 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
591 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
592 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
593 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
594 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
595 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
596 (arc_opcode arc_opcodes): Null terminate the array.
597 (arc_num_opcodes): Remove.
598 * arc-ext.h (INSERT_XOP): Define.
599 (extInstruction_t): Likewise.
600 (arcExtMap_instName): Delete.
601 (arcExtMap_insn): New function.
602 (arcExtMap_genOpcode): Likewise.
603 * arc-ext.c (ExtInstruction): Remove.
604 (create_map): Zero initialize instruction fields.
605 (arcExtMap_instName): Remove.
606 (arcExtMap_insn): New function.
607 (dump_ARC_extmap): More info while debuging.
608 (arcExtMap_genOpcode): New function.
609 * arc-dis.c (find_format): New function.
610 (print_insn_arc): Use find_format.
611 (arc_get_disassembler): Enable dump_ARC_extmap only when
614 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
616 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
617 instruction bits out.
619 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
621 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
622 * arc-opc.c (arc_flag_operands): Add new flags.
623 (arc_flag_classes): Add new classes.
625 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
627 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
629 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
631 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
632 encode1, rflt, crc16, and crc32 instructions.
633 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
634 (arc_flag_classes): Add C_NPS_R.
635 (insert_nps_bitop_size_2b): New function.
636 (extract_nps_bitop_size_2b): Likewise.
637 (insert_nps_bitop_uimm8): Likewise.
638 (extract_nps_bitop_uimm8): Likewise.
639 (arc_operands): Add new operand entries.
641 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
643 * arc-regs.h: Add a new subclass field. Add double assist
644 accumulator register values.
645 * arc-tbl.h: Use DPA subclass to mark the double assist
646 instructions. Use DPX/SPX subclas to mark the FPX instructions.
647 * arc-opc.c (RSP): Define instead of SP.
648 (arc_aux_regs): Add the subclass field.
650 2016-04-05 Jiong Wang <jiong.wang@arm.com>
652 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
654 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
656 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
659 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
661 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
662 issues. No functional changes.
664 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
666 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
667 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
668 (RTT): Remove duplicate.
669 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
670 (PCT_CONFIG*): Remove.
671 (D1L, D1H, D2H, D2L): Define.
673 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
675 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
677 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
679 * arc-tbl.h (invld07): Remove.
680 * arc-ext-tbl.h: New file.
681 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
682 * arc-opc.c (arc_opcodes): Add ext-tbl include.
684 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
686 Fix -Wstack-usage warnings.
687 * aarch64-dis.c (print_operands): Substitute size.
688 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
690 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
692 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
693 to get a proper diagnostic when an invalid ASR register is used.
695 2016-03-22 Nick Clifton <nickc@redhat.com>
697 * configure: Regenerate.
699 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
701 * arc-nps400-tbl.h: New file.
702 * arc-opc.c: Add top level comment.
703 (insert_nps_3bit_dst): New function.
704 (extract_nps_3bit_dst): New function.
705 (insert_nps_3bit_src2): New function.
706 (extract_nps_3bit_src2): New function.
707 (insert_nps_bitop_size): New function.
708 (extract_nps_bitop_size): New function.
709 (arc_flag_operands): Add nps400 entries.
710 (arc_flag_classes): Add nps400 entries.
711 (arc_operands): Add nps400 entries.
712 (arc_opcodes): Add nps400 include.
714 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
716 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
717 the new class enum values.
719 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
721 * arc-dis.c (print_insn_arc): Handle nps400.
723 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
725 * arc-opc.c (BASE): Delete.
727 2016-03-18 Nick Clifton <nickc@redhat.com>
730 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
731 of MOV insn that aliases an ORR insn.
733 2016-03-16 Jiong Wang <jiong.wang@arm.com>
735 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
737 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
739 * mcore-opc.h: Add const qualifiers.
740 * microblaze-opc.h (struct op_code_struct): Likewise.
741 * sh-opc.h: Likewise.
742 * tic4x-dis.c (tic4x_print_indirect): Likewise.
743 (tic4x_print_op): Likewise.
745 2016-03-02 Alan Modra <amodra@gmail.com>
747 * or1k-desc.h: Regenerate.
748 * fr30-ibld.c: Regenerate.
749 * rl78-decode.c: Regenerate.
751 2016-03-01 Nick Clifton <nickc@redhat.com>
754 * rl78-dis.c (print_insn_rl78_common): Fix typo.
756 2016-02-24 Renlin Li <renlin.li@arm.com>
758 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
759 (print_insn_coprocessor): Support fp16 instructions.
761 2016-02-24 Renlin Li <renlin.li@arm.com>
763 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
766 2016-02-24 Renlin Li <renlin.li@arm.com>
768 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
769 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
771 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
773 * i386-dis.c (print_insn): Parenthesize expression to prevent
777 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
778 Janek van Oirschot <jvanoirs@synopsys.com>
780 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
783 2016-02-04 Nick Clifton <nickc@redhat.com>
786 * msp430-dis.c (print_insn_msp430): Add a special case for
787 decoding an RRC instruction with the ZC bit set in the extension
790 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
792 * cgen-ibld.in (insert_normal): Rework calculation of shift.
793 * epiphany-ibld.c: Regenerate.
794 * fr30-ibld.c: Regenerate.
795 * frv-ibld.c: Regenerate.
796 * ip2k-ibld.c: Regenerate.
797 * iq2000-ibld.c: Regenerate.
798 * lm32-ibld.c: Regenerate.
799 * m32c-ibld.c: Regenerate.
800 * m32r-ibld.c: Regenerate.
801 * mep-ibld.c: Regenerate.
802 * mt-ibld.c: Regenerate.
803 * or1k-ibld.c: Regenerate.
804 * xc16x-ibld.c: Regenerate.
805 * xstormy16-ibld.c: Regenerate.
807 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
809 * epiphany-dis.c: Regenerated from latest cpu files.
811 2016-02-01 Michael McConville <mmcco@mykolab.com>
813 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
816 2016-01-25 Renlin Li <renlin.li@arm.com>
818 * arm-dis.c (mapping_symbol_for_insn): New function.
819 (find_ifthen_state): Call mapping_symbol_for_insn().
821 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
823 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
824 of MSR UAO immediate operand.
826 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
828 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
831 2016-01-17 Alan Modra <amodra@gmail.com>
833 * configure: Regenerate.
835 2016-01-14 Nick Clifton <nickc@redhat.com>
837 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
838 instructions that can support stack pointer operations.
839 * rl78-decode.c: Regenerate.
840 * rl78-dis.c: Fix display of stack pointer in MOVW based
843 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
845 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
846 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
847 erxtatus_el1 and erxaddr_el1.
849 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
851 * arm-dis.c (arm_opcodes): Add "esb".
852 (thumb_opcodes): Likewise.
854 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
856 * ppc-opc.c <xscmpnedp>: Delete.
857 <xvcmpnedp>: Likewise.
858 <xvcmpnedp.>: Likewise.
859 <xvcmpnesp>: Likewise.
860 <xvcmpnesp.>: Likewise.
862 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
865 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
868 2016-01-01 Alan Modra <amodra@gmail.com>
870 Update year range in copyright notice of all files.
872 For older changes see ChangeLog-2015
874 Copyright (C) 2016 Free Software Foundation, Inc.
876 Copying and distribution of this file, with or without modification,
877 are permitted in any medium without royalty provided the copyright
878 notice and this notice are preserved.
884 version-control: never