docs: update product names & brand names

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>

diff --git a/docs/edison.md b/docs/edison.md
index 8114afb..e4cc6d0 100644 (file)
--- a/docs/edison.md
+++ b/docs/edison.md
@@ -1,8 +1,8 @@
 Intel Edison                            {#edison}
 =============
 
-Edison is a dual core Silvermont Atom clocked at 500MHz. The Edison
-also features 4GB of storage, 1GB ram and onboard wifi and bluetooth.
+Intel(R) Edison is a dual core Silvermont Atom(TM) clocked at 500MHz. The
+Edison also features 4GB of storage, 1GB ram and onboard wifi and bluetooth.
 
 Currently Supported boards:
 - Intel Arduino board
@@ -25,8 +25,8 @@ in libmraa:
 - AIO pins are treated as 0-5 in mraa_aio_init() but as 14-19 for everything
   else. Therefore use mraa_gpio_init(14) to use A0 as a Gpio
 
-Intel breakout board
---------------------
+Intel(R) breakout board
+-----------------------
 
 - Both I2C buses are avaible 1 & 6
 - IO on the miniboard is 1.8V

diff --git a/docs/galileorevd.md b/docs/galileorevd.md
index 382ee57..16d59d8 100644 (file)
--- a/docs/galileorevd.md
+++ b/docs/galileorevd.md
@@ -1,7 +1,7 @@
 Galileo Gen 1 - Rev D                            {#galileorevd}
 =====================
 
-Galileo is a microcontroller board based on the Intel® Quark SoC X1000
+Galileo is a microcontroller board based on the Intel(R) Quark(TM) SoC X1000
 Application Processor, a 32-bit Intel Pentium-class system on a chip.
 
 The rev D board has the following limitations in libmraa:

diff --git a/docs/galileorevh.md b/docs/galileorevh.md
index 464c9d4..42063f1 100644 (file)
--- a/docs/galileorevh.md
+++ b/docs/galileorevh.md
@@ -1,7 +1,7 @@
 Galileo Gen 2 - Rev H                           {#galileorevh}
 =====================
 
-Galileo is a microcontroller board based on the Intel® Quark SoC X1000
+Galileo is a microcontroller board based on the Intel(R) Quark(TM) SoC X1000
 Application Processor, a 32-bit Intel Pentium-class system on a chip.
 
 The Gen 2 board has the following limitations in libmraa:

diff --git a/docs/intel_de3815.md b/docs/intel_de3815.md
index 60a168f..b032d6f 100644 (file)
--- a/docs/intel_de3815.md
+++ b/docs/intel_de3815.md
@@ -1,7 +1,7 @@
-Intel NUC DE3815tykhe                            {#de3815}
+Intel(R) NUC DE3815tykhe                            {#de3815}
 =============
 
-The DE3815 NUC Kit is a single core Atom clocked at 1.46GHz.
+The DE3815 NUC Kit is a single core Atom(TM) clocked at 1.46GHz.
 http://www.intel.com/content/www/us/en/nuc/nuc-kit-de3815tykhe.html
 
 Interface notes

diff --git a/docs/minnow_max.md b/docs/minnow_max.md
index 4787489..b2d62dd 100644 (file)
--- a/docs/minnow_max.md
+++ b/docs/minnow_max.md
@@ -1,8 +1,10 @@
-Intel Minnowboard Max               {#minnowmax}
-=====================
-MinnowBoard MAX is an open hardware embedded board designed with the Intel® Atom™ E38xx series SOC (known as Bay Trail).
+Intel(R) Minnowboard Max               {#minnowmax}
+========================
+MinnowBoard MAX is an open hardware embedded board designed with the Intel(R)
+Atom(TM) E38xx series SOC (Fromerly Bay Trail).
 
-For product overview and faq see http://www.minnowboard.org/faq-minnowboard-max/
+For product overview and faq see
+http://www.minnowboard.org/faq-minnowboard-max/
 
 For technical details see http://www.elinux.org/Minnowboard:MinnowMax
 
@@ -12,12 +14,13 @@ mraa has only been tested with 64 bit firmware version 0.73 or later.
 
 Interface notes
 ---------------
-The low speed I/O connector supported as per table below. 
-This assumes default BIOS settings, as they are not dynamcially detected 
-If any changes are mode (Device Manager -> System Setup -> South Cluster -> LPSS & CSS) 
-them mraa calls will not behave as expected.
+The low speed I/O connector supported as per table below.  This assumes default
+BIOS settings, as they are not dynamcially detected If any changes are mode
+(Device Manager -> System Setup -> South Cluster -> LPSS & CSS) them mraa calls
+will not behave as expected.
 
-Documentation shows i2c on bus #5, ACPI shows it on bus #6, but driver uses bus #7.
+Documentation shows i2c on bus #5, ACPI shows it on bus #6, but driver uses bus
+#7.
 
 **SPI operation is not currently supported**