2 * Author: Brendan Le Foll <brendan.le.foll@intel.com>
3 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
4 * Copyright (c) 2014 Intel Corporation.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice shall be
15 * included in all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "x86/intel_galileo_rev_g.h"
34 #define SYSFS_CLASS_GPIO "/sys/class/gpio"
35 #define PLATFORM_NAME "Intel Galileo Gen 2"
37 #define UIO_PATH "/dev/uio0"
39 static uint8_t *mmap_reg = NULL;
40 static int mmap_fd = 0;
41 static int mmap_size = 0x1000;
42 static unsigned int mmap_count = 0;
44 static unsigned int pullup_map[] = {33,29,35,17,37,19,21,39,41,23,27,25,43,31,49,51,53,55,57,59};
46 static mraa_gpio_context agpioOutputen[MRAA_INTEL_GALILEO_GEN_2_PINCOUNT];
49 mraa_intel_galileo_gen2_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
51 if (dev->phy_pin >= 0) {
52 int pin = dev->phy_pin;
53 if (plat->pins[pin].gpio.complex_cap.complex_pin != 1)
56 if (plat->pins[pin].gpio.complex_cap.output_en == 1) {
57 if (!agpioOutputen[pin]) {
58 agpioOutputen[pin] = mraa_gpio_init_raw(plat->pins[pin].gpio.output_enable);
59 if (agpioOutputen[pin] == NULL) {
60 return MRAA_ERROR_INVALID_RESOURCE;
62 if (mraa_gpio_dir(agpioOutputen[pin], MRAA_GPIO_OUT) != MRAA_SUCCESS) {
63 return MRAA_ERROR_INVALID_RESOURCE;
68 if (dir == MRAA_GPIO_OUT) {
71 if (mraa_gpio_write(agpioOutputen[pin], output_val) != MRAA_SUCCESS) {
72 return MRAA_ERROR_INVALID_RESOURCE;
80 mraa_intel_galileo_gen2_gpio_close_pre(mraa_gpio_context dev)
82 if (dev->phy_pin >= 0) {
83 int pin = dev->phy_pin;
84 if (agpioOutputen[pin]) {
85 mraa_gpio_close(agpioOutputen[pin]);
86 agpioOutputen[pin] = NULL;
93 mraa_intel_galileo_gen2_i2c_init_pre(unsigned int bus)
95 mraa_gpio_context io18 = mraa_gpio_init_raw(57);
99 return MRAA_ERROR_UNSPECIFIED;
101 status += mraa_gpio_dir(io18, MRAA_GPIO_IN);
102 status += mraa_gpio_mode(io18, MRAA_GPIO_HIZ);
103 mraa_gpio_close(io18);
105 mraa_gpio_context io19 = mraa_gpio_init_raw(59);
107 return MRAA_ERROR_UNSPECIFIED;
109 status += mraa_gpio_dir(io19, MRAA_GPIO_IN);
110 status += mraa_gpio_mode(io19, MRAA_GPIO_HIZ);
111 mraa_gpio_close(io19);
114 return MRAA_ERROR_UNSPECIFIED;
120 mraa_intel_galileo_gen2_pwm_period_replace(mraa_pwm_context dev, int period)
123 snprintf(bu,MAX_SIZE ,"/sys/class/pwm/pwmchip%d/device/pwm_period", dev->chipid);
125 int period_f = open(bu, O_RDWR);
126 if (period_f == -1) {
127 syslog(LOG_ERR, "galileo2: Failed to open period for writing!");
128 return MRAA_ERROR_INVALID_RESOURCE;
131 int length = snprintf(out, MAX_SIZE, "%d", period);
132 if (write(period_f, out, length*sizeof(char)) == -1) {
134 return MRAA_ERROR_INVALID_RESOURCE;
142 mraa_intel_galileo_gen2_gpio_mode_replace(mraa_gpio_context dev, gpio_mode_t mode)
144 if (dev->value_fp != -1) {
145 close(dev->value_fp);
149 mraa_gpio_context pullup_e;
150 pullup_e = mraa_gpio_init_raw(pullup_map[dev->phy_pin]);
151 if (pullup_e == NULL) {
152 return MRAA_ERROR_INVALID_RESOURCE;
154 if (mraa_gpio_dir(pullup_e, MRAA_GPIO_IN) != MRAA_SUCCESS) {
155 mraa_gpio_close(pullup_e);
156 syslog(LOG_ERR, "galileo2: Failed to set gpio pullup");
157 return MRAA_ERROR_INVALID_RESOURCE;
160 char filepath[MAX_SIZE];
161 snprintf(filepath, MAX_SIZE, SYSFS_CLASS_GPIO "/gpio%d/drive", pullup_map[dev->phy_pin]);
163 int drive = open(filepath, O_WRONLY);
165 syslog(LOG_ERR, "galileo2: Failed to open drive for writing");
166 return MRAA_ERROR_INVALID_RESOURCE;
173 case MRAA_GPIO_STRONG:
174 length = snprintf(bu, sizeof(bu), "hiz");
176 case MRAA_GPIO_PULLUP:
177 length = snprintf(bu, sizeof(bu), "strong");
180 case MRAA_GPIO_PULLDOWN:
181 length = snprintf(bu, sizeof(bu), "pulldown");
190 return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
192 if (write(drive, bu, length*sizeof(char)) == -1) {
193 syslog(LOG_ERR, "galileo2: Failed to write to drive mode");
195 mraa_gpio_close(pullup_e);
196 return MRAA_ERROR_INVALID_RESOURCE;
199 mraa_result_t ret = mraa_gpio_dir(pullup_e, MRAA_GPIO_OUT);
200 ret += mraa_gpio_write(pullup_e, value);
201 if (ret != MRAA_SUCCESS) {
202 syslog(LOG_ERR, "galileo2: Error Setting pullup");
204 return MRAA_ERROR_INVALID_RESOURCE;
208 mraa_gpio_close(pullup_e);
214 mraa_intel_galileo_gen2_uart_init_pre(int index)
216 mraa_gpio_context io0_output = mraa_gpio_init_raw(32);
217 if (io0_output == NULL) {
218 return MRAA_ERROR_INVALID_RESOURCE;
220 mraa_gpio_context io1_output = mraa_gpio_init_raw(28);
221 if (io1_output == NULL) {
222 mraa_gpio_close(io0_output);
223 return MRAA_ERROR_INVALID_RESOURCE;
227 status += mraa_gpio_dir(io0_output, MRAA_GPIO_OUT);
228 status += mraa_gpio_dir(io1_output, MRAA_GPIO_OUT);
230 status += mraa_gpio_write(io0_output, 1);
231 status += mraa_gpio_write(io1_output, 0);
233 mraa_gpio_close(io0_output);
234 mraa_gpio_close(io1_output);
237 return MRAA_ERROR_UNSPECIFIED;
243 mraa_intel_galileo_g2_mmap_unsetup()
245 if (mmap_reg == NULL) {
246 syslog(LOG_ERR, "mmap: null register cant unsetup");
247 return MRAA_ERROR_INVALID_RESOURCE;
249 munmap(mmap_reg, mmap_size);
256 mraa_intel_galileo_g2_mmap_write(mraa_gpio_context dev, int value)
258 int bitpos = plat->pins[dev->phy_pin].mmap.bit_pos;
260 *((unsigned *)mmap_reg) |= (1<<bitpos);
263 *((unsigned *)mmap_reg) &= ~(1<<bitpos);
269 mraa_intel_galileo_g2_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
272 syslog(LOG_ERR, "Galileo mmap: context not valid");
273 return MRAA_ERROR_INVALID_HANDLE;
276 if (mraa_pin_mode_test(dev->phy_pin, MRAA_PIN_FAST_GPIO) == 0) {
277 syslog(LOG_ERR, "Galileo mmap: mmap not on this pin");
278 return MRAA_ERROR_NO_RESOURCES;
281 if (dev->mmap_write == NULL) {
282 syslog(LOG_ERR, "mmap: can't disable disabled mmap gpio");
283 return MRAA_ERROR_INVALID_PARAMETER;
285 dev->mmap_write = NULL;
287 if (mmap_count == 0) {
288 return mraa_intel_galileo_g2_mmap_unsetup();
293 if (dev->mmap_write != NULL) {
294 syslog(LOG_ERR, "mmap: can't enable enabled mmap gpio");
295 return MRAA_ERROR_INVALID_PARAMETER;
297 if (mmap_reg == NULL) {
298 if ((mmap_fd = open(UIO_PATH, O_RDWR)) < 0) {
299 syslog(LOG_ERR, "mmap: Unable to open UIO device");
300 return MRAA_ERROR_INVALID_RESOURCE;
302 mmap_reg = mmap(NULL, mmap_size, PROT_READ|PROT_WRITE,
303 MAP_SHARED, mmap_fd, 0);
305 if (mmap_reg == MAP_FAILED) {
306 syslog(LOG_ERR, "mmap: failed to mmap");
309 return MRAA_ERROR_NO_RESOURCES;
312 if (mraa_setup_mux_mapped(plat->pins[dev->phy_pin].mmap.gpio)
314 syslog(LOG_ERR, "mmap: unable to setup required multiplexers");
315 return MRAA_ERROR_INVALID_RESOURCE;
317 dev->mmap_write = &mraa_intel_galileo_g2_mmap_write;
322 mraa_intel_galileo_gen2()
324 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
329 b->platform_name = PLATFORM_NAME;
330 b->phy_pin_count = 20;
334 b->adc_supported = 10;
335 b->pwm_default_period = 5000;
336 b->pwm_max_period = 41666;
337 b->pwm_min_period = 666;
339 advance_func->gpio_close_pre = &mraa_intel_galileo_gen2_gpio_close_pre;
340 advance_func->gpio_dir_pre = &mraa_intel_galileo_gen2_dir_pre;
341 advance_func->i2c_init_pre = &mraa_intel_galileo_gen2_i2c_init_pre;
342 advance_func->pwm_period_replace = &mraa_intel_galileo_gen2_pwm_period_replace;
343 advance_func->gpio_mode_replace = &mraa_intel_galileo_gen2_gpio_mode_replace;
344 advance_func->uart_init_pre = &mraa_intel_galileo_gen2_uart_init_pre;
345 advance_func->gpio_mmap_setup = &mraa_intel_galileo_g2_mmap_setup;
347 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_GEN_2_PINCOUNT);
348 if (b->pins == NULL) {
352 strncpy(b->pins[0].name, "IO0", 8);
353 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,1};
354 b->pins[0].gpio.pinmap = 11;
355 b->pins[0].gpio.parent_id = 0;
356 b->pins[0].gpio.mux_total = 0;
357 b->pins[0].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
358 b->pins[0].gpio.output_enable = 32;
359 b->pins[0].gpio.pullup_enable = 33;
360 b->pins[0].mmap.gpio.pinmap = 11;
361 strncpy(b->pins[0].mmap.mem_dev, "/dev/uio0", 12);
362 b->pins[0].mmap.gpio.mux_total = 2;
363 b->pins[0].mmap.gpio.mux[0].pin = 32;
364 b->pins[0].mmap.gpio.mux[0].value = 0;
365 b->pins[0].mmap.gpio.mux[1].pin = 11;
366 b->pins[0].mmap.gpio.mux[1].value = 0;
367 b->pins[0].mmap.mem_sz = 0x1000;
368 b->pins[0].mmap.bit_pos = 3;
369 b->pins[0].uart.parent_id = 0;
370 b->pins[0].uart.mux_total = 0;
372 strncpy(b->pins[1].name, "IO1", 8);
373 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,1};
374 b->pins[1].gpio.pinmap = 12;
375 b->pins[1].gpio.parent_id = 0;
376 b->pins[1].gpio.mux_total = 1;
377 b->pins[1].gpio.mux[0].pin = 45;
378 b->pins[1].gpio.mux[0].value = 0;
379 b->pins[1].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
380 b->pins[1].gpio.output_enable = 28;
381 b->pins[1].gpio.pullup_enable = 29;
382 b->pins[1].mmap.gpio.pinmap = 12;
383 strncpy(b->pins[1].mmap.mem_dev, "/dev/uio0", 12);
384 b->pins[1].mmap.gpio.mux_total = 3;
385 b->pins[1].mmap.gpio.mux[0].pin = 45;
386 b->pins[1].mmap.gpio.mux[0].value = 0;
387 b->pins[1].mmap.gpio.mux[1].pin = 28;
388 b->pins[1].mmap.gpio.mux[1].value = 0;
389 b->pins[1].mmap.gpio.mux[2].pin = 12;
390 b->pins[1].mmap.gpio.mux[2].value = 0;
391 b->pins[1].mmap.mem_sz = 0x1000;
392 b->pins[1].mmap.bit_pos = 4;
393 b->pins[1].uart.parent_id = 0;
394 b->pins[1].uart.mux_total = 1;
395 b->pins[1].uart.mux[0].pin = 45;
396 b->pins[1].uart.mux[0].value = 1;
398 strncpy(b->pins[2].name, "IO2", 8);
399 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0};
400 b->pins[2].gpio.pinmap = 13;
401 b->pins[2].gpio.parent_id = 0;
402 b->pins[2].gpio.mux_total = 1;
403 b->pins[2].gpio.mux[0].pin = 77;
404 b->pins[2].gpio.mux[0].value = 0;
405 b->pins[2].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
406 b->pins[2].gpio.output_enable = 34;
407 b->pins[2].gpio.pullup_enable = 35;
408 b->pins[2].mmap.gpio.pinmap = 13;
409 strncpy(b->pins[2].mmap.mem_dev, "/dev/uio0", 12);
410 b->pins[2].mmap.gpio.mux_total = 3;
411 b->pins[2].mmap.gpio.mux[0].pin = 77;
412 b->pins[2].mmap.gpio.mux[0].value = 0;
413 b->pins[2].mmap.gpio.mux[1].pin = 34;
414 b->pins[2].mmap.gpio.mux[1].value = 0;
415 b->pins[2].mmap.gpio.mux[2].pin = 13;
416 b->pins[2].mmap.gpio.mux[2].value = 0;
417 b->pins[2].mmap.mem_sz = 0x1000;
418 b->pins[2].mmap.bit_pos = 5;
420 strncpy(b->pins[3].name, "IO3", 8);
421 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,1,0,0,0};
422 b->pins[3].gpio.pinmap = 14;
423 b->pins[3].gpio.parent_id = 0;
424 b->pins[3].gpio.mux_total = 2;
425 b->pins[3].gpio.mux[0].pin = 76;
426 b->pins[3].gpio.mux[0].value = 0;
427 b->pins[3].gpio.mux[1].pin = 64;
428 b->pins[3].gpio.mux[1].value = 0;
429 b->pins[3].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
430 b->pins[3].gpio.output_enable = 16;
431 b->pins[3].gpio.pullup_enable = 17;
432 b->pins[3].pwm.pinmap = 1;
433 b->pins[3].pwm.parent_id = 0;
434 b->pins[3].pwm.mux_total = 3;
435 b->pins[3].pwm.mux[0].pin = 76;
436 b->pins[3].pwm.mux[0].value = 0;
437 b->pins[3].pwm.mux[1].pin = 64;
438 b->pins[3].pwm.mux[1].value = 1;
439 b->pins[3].pwm.mux[2].pin = 16;
440 b->pins[3].pwm.mux[2].value = 0;
441 b->pins[3].mmap.gpio.pinmap = 14;
442 strncpy(b->pins[3].mmap.mem_dev, "/dev/uio0", 12);
443 b->pins[3].mmap.gpio.mux_total = 4;
444 b->pins[3].mmap.gpio.mux[0].pin = 76;
445 b->pins[3].mmap.gpio.mux[0].value = 0;
446 b->pins[3].mmap.gpio.mux[1].pin = 64;
447 b->pins[3].mmap.gpio.mux[1].value = 0;
448 b->pins[3].mmap.gpio.mux[2].pin = 16;
449 b->pins[3].mmap.gpio.mux[2].value = 0;
450 b->pins[3].mmap.gpio.mux[3].pin = 14;
451 b->pins[3].mmap.gpio.mux[3].value = 0;
452 b->pins[3].mmap.mem_sz = 0x1000;
453 b->pins[3].mmap.bit_pos = 6;
455 strncpy(b->pins[4].name, "IO4", 8);
456 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
457 b->pins[4].gpio.pinmap = 6;
458 b->pins[4].gpio.parent_id = 0;
459 b->pins[4].gpio.mux_total = 0;
460 b->pins[4].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
461 b->pins[4].gpio.output_enable = 36;
462 b->pins[4].gpio.pullup_enable = 37;
464 strncpy(b->pins[5].name, "IO5", 8);
465 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
466 b->pins[5].gpio.pinmap = 0;
467 b->pins[5].gpio.parent_id = 0;
468 b->pins[5].gpio.mux_total = 1;
469 b->pins[5].gpio.mux[0].pin = 66;
470 b->pins[5].gpio.mux[0].value = 0;
471 b->pins[5].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
472 b->pins[5].gpio.output_enable = 18;
473 b->pins[5].gpio.pullup_enable = 19;
474 b->pins[5].pwm.pinmap = 3;
475 b->pins[5].pwm.parent_id = 0;
476 b->pins[5].pwm.mux_total = 2;
477 b->pins[5].pwm.mux[0].pin = 66;
478 b->pins[5].pwm.mux[0].value = 1;
479 b->pins[5].pwm.mux[1].pin = 18;
480 b->pins[5].pwm.mux[1].value = 0;
482 strncpy(b->pins[6].name, "IO6", 8);
483 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
484 b->pins[6].gpio.pinmap = 1;
485 b->pins[6].gpio.parent_id = 0;
486 b->pins[6].gpio.mux_total = 1;
487 b->pins[6].gpio.mux[0].pin = 68;
488 b->pins[6].gpio.mux[0].value = 0;
489 b->pins[6].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
490 b->pins[6].gpio.output_enable = 20;
491 b->pins[6].gpio.pullup_enable = 21;
492 b->pins[6].pwm.pinmap = 5;
493 b->pins[6].pwm.parent_id = 0;
494 b->pins[6].pwm.mux_total = 2;
495 b->pins[6].pwm.mux[0].pin = 68;
496 b->pins[6].pwm.mux[0].value = 1;
497 b->pins[6].pwm.mux[1].pin = 20;
498 b->pins[6].pwm.mux[1].value = 0;
500 strncpy(b->pins[7].name, "IO7", 8);
501 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
502 b->pins[7].gpio.pinmap = 38;
503 b->pins[7].gpio.parent_id = 0;
504 b->pins[7].gpio.mux_total = 0;
505 b->pins[7].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
506 b->pins[7].gpio.pullup_enable = 39;
508 strncpy(b->pins[8].name, "IO8", 8);
509 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
510 b->pins[8].gpio.pinmap = 40;
511 b->pins[8].gpio.parent_id = 0;
512 b->pins[8].gpio.mux_total = 0;
513 b->pins[8].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
514 b->pins[8].gpio.pullup_enable = 41;
516 strncpy(b->pins[9].name, "IO9", 8);
517 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
518 b->pins[9].gpio.pinmap = 4;
519 b->pins[9].gpio.parent_id = 0;
520 b->pins[9].gpio.mux_total = 1;
521 b->pins[9].gpio.mux[0].pin = 70;
522 b->pins[9].gpio.mux[0].value = 0;
523 b->pins[9].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
524 b->pins[9].gpio.output_enable = 22;
525 b->pins[9].gpio.pullup_enable = 23;
526 b->pins[9].pwm.pinmap = 7;
527 b->pins[9].pwm.parent_id = 0;
528 b->pins[9].pwm.mux_total = 2;
529 b->pins[9].pwm.mux[0].pin = 70;
530 b->pins[9].pwm.mux[0].value = 1;
531 b->pins[9].pwm.mux[1].pin = 22;
532 b->pins[9].pwm.mux[1].value = 0;
534 strncpy(b->pins[10].name, "IO10", 8);
535 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,1,1,1,0,0};
536 b->pins[10].gpio.pinmap = 10;
537 b->pins[10].gpio.parent_id = 0;
538 b->pins[10].gpio.mux_total = 1;
539 b->pins[10].gpio.mux[0].pin = 74;
540 b->pins[10].gpio.mux[0].value = 0;
541 b->pins[10].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
542 b->pins[10].gpio.output_enable = 26;
543 b->pins[10].gpio.pullup_enable = 27;
544 b->pins[10].pwm.pinmap = 11;
545 b->pins[10].pwm.parent_id = 0;
546 b->pins[10].pwm.mux_total = 2;
547 b->pins[10].pwm.mux[0].pin = 74;
548 b->pins[10].pwm.mux[0].value = 1;
549 b->pins[10].pwm.mux[1].pin = 26;
550 b->pins[10].pwm.mux[1].value = 0;
551 b->pins[10].mmap.gpio.pinmap = 10;
552 strncpy(b->pins[10].mmap.mem_dev, "/dev/uio0", 12);
553 b->pins[10].mmap.gpio.mux_total = 3;
554 b->pins[10].mmap.gpio.mux[0].pin = 74;
555 b->pins[10].mmap.gpio.mux[0].value = 0;
556 b->pins[10].mmap.gpio.mux[1].pin = 26;
557 b->pins[10].mmap.gpio.mux[1].value = 0;
558 b->pins[10].mmap.gpio.mux[2].pin = 10;
559 b->pins[10].mmap.gpio.mux[2].value = 0;
560 b->pins[10].mmap.mem_sz = 0x1000;
561 b->pins[10].mmap.bit_pos = 2;
562 b->pins[10].spi.parent_id = 1;
563 b->pins[10].spi.mux_total = 1;
564 b->pins[10].spi.mux[0].pin = 74;
565 b->pins[10].spi.mux[0].value = 0;
567 strncpy(b->pins[11].name, "IO11", 8);
568 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0};
569 b->pins[11].gpio.pinmap = 5;
570 b->pins[11].gpio.parent_id = 0;
571 b->pins[11].gpio.mux_total = 2;
572 b->pins[11].gpio.mux[0].pin = 72;
573 b->pins[11].gpio.mux[0].value = 0;
574 b->pins[11].gpio.mux[1].pin = 44;
575 b->pins[11].gpio.mux[1].value = 0;
576 b->pins[11].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
577 b->pins[11].gpio.output_enable = 24;
578 b->pins[11].gpio.pullup_enable = 25;
579 b->pins[11].pwm.pinmap = 9;
580 b->pins[11].pwm.parent_id = 0;
581 b->pins[11].pwm.mux_total = 3;
582 b->pins[11].pwm.mux[0].pin = 72;
583 b->pins[11].pwm.mux[0].value = 1;
584 b->pins[11].pwm.mux[1].pin = 44;
585 b->pins[11].pwm.mux[1].value = 0;
586 b->pins[11].pwm.mux[2].pin = 24;
587 b->pins[11].pwm.mux[2].value = 0;
588 b->pins[11].spi.pinmap = 1;
589 b->pins[11].spi.mux_total = 3;
590 b->pins[11].spi.mux[0].pin = 72;
591 b->pins[11].spi.mux[0].value = 0;
592 b->pins[11].spi.mux[1].pin = 44;
593 b->pins[11].spi.mux[1].value = 1;
594 b->pins[11].spi.mux[2].pin = 24;
595 b->pins[11].spi.mux[2].value = 0;
597 strncpy(b->pins[12].name, "IO12", 8);
598 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,1,1,0,0};
599 b->pins[12].gpio.pinmap = 15;
600 b->pins[12].gpio.parent_id = 0;
601 b->pins[12].gpio.mux_total = 0;
602 b->pins[12].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
603 b->pins[12].gpio.output_enable = 42;
604 b->pins[12].gpio.pullup_enable = 43;
605 b->pins[12].spi.pinmap = 1;
606 b->pins[12].spi.mux_total = 1;
607 b->pins[12].spi.mux[0].pin = 42;
608 b->pins[12].spi.mux[0].value = 1;
609 b->pins[12].mmap.gpio.pinmap = 15;
610 strncpy(b->pins[12].mmap.mem_dev, "/dev/uio0", 12);
611 b->pins[12].mmap.gpio.mux_total = 2;
612 b->pins[12].mmap.gpio.mux[0].pin = 42;
613 b->pins[12].mmap.gpio.mux[0].value = 0;
614 b->pins[12].mmap.gpio.mux[1].pin = 15;
615 b->pins[12].mmap.gpio.mux[1].value = 0;
616 b->pins[12].mmap.mem_sz = 0x1000;
617 b->pins[12].mmap.bit_pos = 7;
619 strncpy(b->pins[13].name, "IO13", 8);
620 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0};
621 b->pins[13].gpio.pinmap = 7;
622 b->pins[13].gpio.parent_id = 0;
623 b->pins[13].gpio.mux_total = 1;
624 b->pins[13].gpio.mux[0].pin = 46;
625 b->pins[13].gpio.mux[0].value = 0;
626 b->pins[13].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
627 b->pins[13].gpio.output_enable = 30;
628 b->pins[13].gpio.pullup_enable = 31;
629 b->pins[13].spi.pinmap = 1;
630 b->pins[13].spi.mux_total = 2;
631 b->pins[13].spi.mux[0].pin = 46;
632 b->pins[13].spi.mux[0].value = 1;
633 b->pins[13].spi.mux[1].pin = 30;
634 b->pins[13].spi.mux[1].value = 0;
637 strncpy(b->pins[14].name, "A0", 8);
638 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
639 b->pins[14].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
640 b->pins[14].gpio.pullup_enable = 49;
641 b->pins[14].aio.pinmap = 0;
642 b->pins[14].aio.mux_total = 1;
643 b->pins[14].aio.mux[0].pin = 49;
644 b->pins[14].aio.mux[0].value = 1;
645 b->pins[14].gpio.pinmap = 48;
646 b->pins[14].gpio.mux_total = 0;
648 strncpy(b->pins[15].name, "A1", 8);
649 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
650 b->pins[15].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
651 b->pins[15].gpio.pullup_enable = 51;
652 b->pins[15].aio.pinmap = 1;
653 b->pins[15].aio.mux[0].pin = 51;
654 b->pins[15].aio.mux[0].value = 1;
655 b->pins[15].aio.mux_total = 0;
656 b->pins[15].gpio.pinmap = 50;
657 b->pins[15].gpio.mux_total = 0;
659 strncpy(b->pins[16].name, "A2", 8);
660 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
661 b->pins[16].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
662 b->pins[16].gpio.pullup_enable = 53;
663 b->pins[16].aio.pinmap = 2;
664 b->pins[16].aio.mux_total = 1;
665 b->pins[16].aio.mux[0].pin = 53;
666 b->pins[16].aio.mux[0].value = 1;
667 b->pins[16].gpio.pinmap = 52;
668 b->pins[16].gpio.mux_total = 0;
670 strncpy(b->pins[17].name, "A3", 8);
671 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
672 b->pins[17].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
673 b->pins[17].gpio.pullup_enable = 55;
674 b->pins[17].aio.pinmap = 3;
675 b->pins[17].aio.mux_total = 1;
676 b->pins[17].aio.mux[0].pin = 55;
677 b->pins[17].aio.mux[0].value = 1;
678 b->pins[17].gpio.pinmap = 54;
679 b->pins[17].gpio.mux_total = 0;
681 strncpy(b->pins[18].name, "A4", 8);
682 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1};
683 b->pins[18].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
684 b->pins[18].gpio.pullup_enable = 57;
685 b->pins[18].i2c.pinmap = 1;
686 b->pins[18].i2c.mux_total = 1;
687 b->pins[18].i2c.mux[0].pin = 60;
688 b->pins[18].i2c.mux[0].value = 0;
689 b->pins[18].aio.pinmap = 4;
690 b->pins[18].aio.mux_total = 3;
691 b->pins[18].aio.mux[0].pin = 60;
692 b->pins[18].aio.mux[0].value = 1;
693 b->pins[18].aio.mux[1].pin = 78;
694 b->pins[18].aio.mux[1].value = 0;
695 b->pins[18].aio.mux[2].pin = 57;
696 b->pins[18].aio.mux[2].value = 0;
697 b->pins[18].gpio.pinmap = 56;
698 b->pins[18].gpio.mux_total = 2;
699 b->pins[18].gpio.mux[0].pin = 60;
700 b->pins[18].gpio.mux[0].value = 1;
701 b->pins[18].gpio.mux[1].pin = 78;
702 b->pins[18].gpio.mux[1].value = 1;
704 strncpy(b->pins[19].name, "A5", 8);
705 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1};
706 b->pins[19].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
707 b->pins[19].gpio.pullup_enable = 59;
708 b->pins[19].i2c.pinmap = 1;
709 b->pins[19].i2c.mux_total = 1;
710 b->pins[19].i2c.mux[0].pin = 60;
711 b->pins[19].i2c.mux[0].value = 0;
712 b->pins[19].aio.pinmap = 5;
713 b->pins[19].aio.mux_total = 3;
714 b->pins[19].aio.mux[0].pin = 60;
715 b->pins[19].aio.mux[0].value = 1;
716 b->pins[19].aio.mux[1].pin = 79;
717 b->pins[19].aio.mux[1].value = 0;
718 b->pins[19].aio.mux[2].pin = 59;
719 b->pins[19].aio.mux[2].value = 1;
720 b->pins[19].gpio.pinmap = 58;
721 b->pins[19].gpio.mux_total = 2;
722 b->pins[19].gpio.mux[0].pin = 60;
723 b->pins[19].gpio.mux[0].value = 1;
724 b->pins[19].gpio.mux[1].pin = 79;
725 b->pins[19].gpio.mux[1].value = 1;
728 b->i2c_bus_count = 1;
730 b->i2c_bus[0].bus_id = 0;
731 b->i2c_bus[0].sda = 18;
732 b->i2c_bus[0].scl = 19;
734 b->spi_bus_count = 1;
736 b->spi_bus[0].bus_id = 1;
737 b->spi_bus[0].slave_s = 0;
738 b->spi_bus[0].cs = 10;
739 b->spi_bus[0].mosi = 11;
740 b->spi_bus[0].miso = 12;
741 b->spi_bus[0].sclk = 13;
743 b->uart_dev_count = 1;
745 b->uart_dev[0].rx = 0;
746 b->uart_dev[0].tx = 1;
747 b->uart_dev[0].device_path = "/dev/ttyS0";
751 syslog(LOG_CRIT, "galileo2: Platform failed to initialise");